PCIe 物理尺寸和形状

1. PCIe Riser (PCIe 插槽)

PowerEdge R7625 机架式服务器 - 高级定制服务
https://www.dell.com/zh-cn/shop/cty/pdp/spd/poweredge-r7625/asper7625
https://www.dell.com/en-us/shop/ipovw/poweredge-r7625
https://www.dell.com/en-us/shop/servers-storage-and-networking/poweredge-r7625-rack-server/spd/poweredge-r7625/pe_r7625_tm_vi_vp_sb
https://www.dell.com/en-us/shop/servers-storage-and-networking/poweredge-r7625-rack-server/spd/poweredge-r7625/pe_r7625_vi_vp_sb_deals

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2. Riser 卡与 PCIe 卡

H3C UniServer B5700 G5刀片服务器 用户指南-6W107
https://www.h3c.com/cn/d_202312/1987607_30005_0.htm

2.1. PCIe 卡尺寸

简称全称Description
LP 卡Low Profile card小尺寸卡
FHHL 卡Full Height, Half Length card全高半长卡
FHFL 卡Full Height, Full Length card全高全长卡
HHHL 卡Half Height, Half Length card半高半长卡
HHFL 卡Half Height, Full Length card半高全长卡
Full Length, FL:全长
Half Length, HL:半长
Full Height, FH:全高
Half Height, HH:半高

PCIe 插槽或接口 PCIe3.0 x16 (16,8,4,2,1)

PCIe 3.0:第三代信号速率
x16:连接器宽度 / 插槽宽度
(16,8,4,2,1):兼容的总线带宽 / 链路宽度,包括 x16,x8,x4,x2 和 x1

3. Form factors (规格,物理尺寸和形状)

NVIDIA A10 Tensor Core GPU
https://www.nvidia.com/en-us/data-center/products/a10-gpu/

Form factors - Single-slot, full-height, full-length (FHFL)

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4. Peripheral Component Interconnect Express (PCI Express, PCIe or PCI-e)

The PCI Express bus is a backwards compatible, high performance, general purpose I/O interconnect bus, and was designed for a range of computing platforms.

The PCI Express bus connects each device directly to the CPU and other system devices through a pair of high speed unidirectional differential links (transmit and recieve, respectively).

PCIe x4 features four PCIe lanes.

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PCIe x1: 1 lane, 18 pins, and 25 mm in length
PCIe x4: 4 lanes, 32 pins, and 39 mm in length
PCIe x8: 8 lanes, 49 pins, and 56 mm in length
PCIe x16: 16 lanes, 82 pins, and 89 mm in length

5. HHHL and FHHL

NVIDIA BlueField-2 InfiniBand/Ethernet DPU User Guide
https://docs.nvidia.com/networking/display/bluefield2dpuvpi/supported+interfaces

Half Height, Half Length, HHHL:半高半长
Full Height, Half Length, FHHL:全高半长

5.1. HHHL DPU Layout and Interface Information

PCI Express Interface: PCIe Gen 4.0 through an x16 edge connector

Half Height, Half Length, HHHL:半高半长
  • Component Side

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  • Print Side

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5.2. FHHL DPU Layout and Interface Information

PCI Express Interface: PCIe Gen 4.0 through an x16 edge connector

Full Height, Half Length, FHHL:全高半长
  • Component Side

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  • Print Side

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6. 英制单位

中文英文缩写复数符号转换
英尺footftfeet'1 foot = 30.48 cm = 12 inches
英寸inchininches"1 inch = 2.54 cm

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3.5 " = 3.5 * 25.4 mm = 88.9 mm
17.2 " = 17.2 * 25.4 mm = 436.88 mm
27.76 " = 27.76 * 25.4 mm = 705.104 mm

6.1. NVIDIA RTX A5500 Graphics Card

https://www.nvidia.com/en-au/design-visualization/rtx-a5500/

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PCIe Gen4 / Active Fan / Dual Slot / FHFL, 4.4"(H) x 10.5"(L)
Form Factor: 4.4" (H) x 10.5" (L) Dual Slot

4.4" = 4.4 * 25.4 mm = 111.76 mm
10.5" = 10.5 * 25.4 mm = 266.7 mm
Full Height Full Length, FHFL:全高全长

6.2. NVIDIA A100 Tensor Core GPU

https://www.nvidia.com/en-us/data-center/a100/

The NVIDIA A100 80GB PCIe card conforms to NVIDIA Form Factor 5.0 specification for a fullheight, full-length (FHFL) dual-slot PCIe card.

NVIDIA A100 80GB PCIe GPU - Product Brief

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6.3. NVIDIA T4

https://www.nvidia.com/en-us/data-center/tesla-t4/

The NVIDIA T4 board is a half-height, half-length card.

NVIDIA T4 70W LOW PROFILE PCIe GPU ACCELERATOR - Product Brief

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References

[1] Yongqiang Cheng, https://yongqiang.blog.csdn.net/

Traditional multi-drop, parallel bus technology is approaching its practical performance limits. It is clear that balancing system performance requires I/O bandwidth to scale with processing and application demands. There is an industry mandate to re-engineer I/O connectivity within cost constraints. PCI Express comprehends the many I/O requirements presented across the spectrum of computing and communications platforms, and rolls them into a common scalable and extensible I/O industry specification. Alongside these increasing performance demands, the enterprise server and communications markets have the need for improved reliability, security, and quality of service guarantees. This specification will therefore be applicable to multiple market segments. Technology advances in high-speed, point-to-point interconnects enable us to break away from the bandwidth limitations of multi-drop, parallel buses. The PCI Express basic physical layer consists of a differential transmit pair and a differential receive pair. Dual simplex data on these point-to-point connections is self-clocked and its bandwidth increases linearly with interconnect width and frequency. PCI Express takes an additional step of including a message space within its bus protocol that is used to implement legacy “side- band” signals. This further reduction of signal pins produces a very low pin count connection for components and adapters. The PCI Express Transaction, Data Link, and Physical Layers are optimized for chip-to-chip and board-to-board interconnect applications. An inherent limitation of today’s PCI-based platforms is the lack of support for isochronous data delivery, an attribute that is especially important to streaming media applications. To enable these emerging applications, PCI Express adds a virtual channel mechanism. In addition to use for support of isochronous traffic, the virtual channel mechanism provides an infrastructure for future extensions in supporting new applications. By adhering to the PCI Software Model, today’s applications are easily migrated even as emerging applications are enabled.
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