Parallel to Serial (可以设置任意位宽)

Reference：

“Digital VLSI Design with Verilog”, John Williams, Springer, 2008.

Page 78 – 80.

1、Verilog Code

SerClock：a Serial Clock input;

ParValid: indicate when data on the parallel bus are stable and valid;

SerValidFlag: Clock out the data high-order bit (MSB) first, one bit per serial clock, setting a SerValidFlag when the first bit is on the serial bus and clearing it after the last bit is on the serial bus.

Done: use it to hold the state of the serialization.

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`timescale 1ns / 1ps
//
// Company: SEU.IC
// Engineer: Ray
//
// Create Date:    15:27:50 04/03/2011
// Design Name:
// Module Name:    par_to_ser_2
//