硬件FPGA实现H.265解码统计

H.265产品信息统计：

1、德国HHI 【统计时间：2014-7-26】

产品主页：

http://www.hhi.fraunhofer.de/fields-of-competence/image-processing/solutions/hevc-software-and-hardware-solutions/hevc-real-time-hardware-decoder.html

 FPGA型号：Altera Stratix V FPGA【Altera 高端FPGA 开发板大致 2万人民币】

FPGA官网主页：http://www.altera.com.cn/devices/fpga/stratix-fpgas/stratix-v/stxv-index.jsp

FPGA 开发板主页：http://www.altera.com.cn/products/devkits/stratix-index.jsp

在150MHz，能够解码1080P@60 ，最高码率为80Mbit/s

需要占用70K ALM资源【Altera Stratix V 有 200K ALM 】

• HEVC Main Profile conformance
• 1080p60 real-time decoding up to 80 Mbit/s on SoA FPGAs
• Core clock frequency 150 Mhz
• Fully hardwired implementation
• No need for additional processor core
• IP Core available as FPGA netlist or VHDL code
• Standard interfaces for easy SoC integration
• Low logic utilization approx. 70k ALM^*
• Codecs are customizable for special applications (like low latency) of existing hardware

_{* Altera Stratix V ALMs}

2、中国芯原 【统计时间：2014-7-26】

产品主页：http://www.verisilicon.com/IPPortfolio_cn_14_99_2_HantroG2.html

支持4K@60fps 解码，同时支持H.265和VP9标准

频率225MHz--4K@60fps

频率32MHz--1080P@30fps

100mW功耗

硬件IP，需要100万门

最多可以同时解码 8路1080P@30fps

• HEVC Main Profile
  • VP9 support will be added later this year
• Supported image size up to 4096x4096
• Reference frame compression to optimize the memory bandwidth
• Legacy formats supported through Hantro H1 Encoder
  • H1 and H2 under common top-level using shared SRAM
• Full hardware implementation
  • Ultra low power consumption
  • Completely off-loads the system CPU
• High DRAM latency resilience up to 1000 cycles