4位比较器

最新推荐文章于 2024-07-11 22:00:00 发布

coolsunxu

最新推荐文章于 2024-07-11 22:00:00 发布

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分类专栏： Verilog 文章标签： verilog 比较器

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module compare_1(
	input wire G_in,L_in,
	input wire x,y,
	output wire G_out,E_out,L_out
);

	reg Gn_out,En_out,Ln_out;//作为运算结果
	always @(*) begin  //*******
		Gn_out<=x&~y|x&G_in|~y&G_in;
		En_out<=~x&~y&~G_in&~L_in|x&y&~G_in&~L_in;
		Ln_out<=~x&y|~x&L_in|y&L_in;
	end
	assign G_out=Gn_out;
	assign E_out=En_out;
	assign L_out=Ln_out;
endmodule

module compare_4(
	input wire[3:0] x,
	input wire[3:0] y,
	input wire G0,L0,
	output wire G_out,E_out,L_out
);
	wire [2:0]G;
	wire [3:0]L;//内在信号
	
	//实例化
	compare_1 C1(.G_in(G0),
							 .L_in(L0),
							 .x(x[0]),
							 .y(y[0]),
							 .G_out(G[0]),
							 .L_out(L[0])
							 );
							 
	compare_1 C2(.G_in(G[0]),
							 .L_in(L[0]),
							 .x(x[1]),
							 .y(y[1]),
							 .G_out(G[1]),
							 .L_out(L[1])
							 );
							 
	compare_1 C3(.G_in(G[1]),
							 .L_in(L[1]),
							 .x(x[2]),
							 .y(y[2]),
							 .G_out(G[2]),
							 .L_out(L[2])
							 );
							 
	compare_1 C4(.G_in(G[2]),
							 .L_in(L[2]),
							 .x(x[3]),
							 .y(y[3]),
							 .G_out(G_out),
							 .E_out(E_out),
							 .L_out(L_out)
							 );
endmodule

module compare_4_tb;
   reg [3:0] x;
   reg [3:0] y;
   reg G0,L0;
   wire G_out,E_out,L_out;
   compare_4 infect(.x(x),
                                   .y(y),
                                   .G0(G0),
                                   .L0(L0),
                                   .G_out(G_out),
                                   .E_out(E_out),
                                   .L_out(L_out)
   );

   initial begin
       x=4'b1100;y=4'b1111;G0=0;L0=0;#100;
       x=4'b1100;y=4'b0011;G0=0;L0=0;#100;
       x=4'b0001;y=4'b0000;G0=0;L0=0;#100;
       x=4'b100;y=4'b1001;G0=0;L0=0;#100;

   end
endmodule