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RSS订阅原创 8位乘法器
module mul8v (a,b,q); input[7:0] a,b; output[15:0] q; assign q=a*b;endmodule
2010-10-12 10:45:00
2383
原创 8位乘法器
LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY mul ISPORT(a,b:IN integer range 0 to 255; q:OUT integer range 0 to 65535);END mul;ARCHITECTURE one OF mul ISBEGINqEND one;
2010-10-12 10:42:00
2039
原创 锁存器
LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY latch1 ISPORT(d:IN STD_LOGIC; ena:IN STD_LOGIC; q:OUT STD_LOGIC);END latch1;ARCHITECTURE example4 OF latch1 ISBEGIN PROCESS(d,ena)
2010-10-09 11:26:00
486
原创 2选1数据选择器
LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY mux21 ISPORT(a,b:IN STD_LOGIC; s:IN STD_LOGIC; y:OUT STD_LOGIC);END mux21;ARCHITECTURE example3 OF mux21 ISBEGINyEND example3;
2010-10-09 11:25:00
4747
原创 半加器
LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY h_adder ISPORT(a,b:IN STD_LOGIC; so,co:OUT STD_LOGIC);END h_adder;ARCHITECTURE example2 OF h_adder ISBEGINsocoEND example2;
2010-10-09 11:24:00
905
1
原创 或门
LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY or1 ISPORT(a,b:IN STD_LOGIC; y:OUT STD_LOGIC);END or1;ARCHITECTURE example1 OF or1 ISBEGIN yEND example1;
2010-10-09 11:22:00
458
原创 8-3编程器
LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY encoder8_3 IS PORT(RESET:IN STD_LOGIC; INPUT:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
2010-10-08 10:12:00
411
原创 4位二进制计数器VHDL源程序
LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY cnt4e ISPORT(clk,ena:IN STD_LOGIC; cout:OUT STD_LOGIC; q:BUFFER INTEGER RANGE 0 TO 15);END cnt4e;ARCHITECTURE one OF cnt4
2010-10-04 20:54:00
12466
1
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