4位二进制计数器VHDL源程序

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY cnt4e IS
PORT(clk,ena:IN STD_LOGIC;
        cout:OUT STD_LOGIC;
           q:BUFFER INTEGER RANGE 0 TO 15);
END cnt4e;
ARCHITECTURE one OF cnt4e IS
BEGIN
        PROCESS(clk,ena)
BEGIN
          IF clk'EVENT AND clk='1' THEN
                IF ena='1' THEN
                     IF q=15 THEN q<=0;
                                cout<='0';
                         ELSIF q=14 THEN q<=q+1;
                                   cout<='1';
                          ELSE q<=q+1;
                     END IF;
                END IF;
           END IF;
        END PROCESS;
END one;