LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY or1 IS
PORT(a,b:IN STD_LOGIC;
y:OUT STD_LOGIC);
END or1;
ARCHITECTURE example1 OF or1 IS
BEGIN
y<=a OR b;
END example1;
或门
最新推荐文章于 2021-10-30 00:12:02 发布
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY or1 IS
PORT(a,b:IN STD_LOGIC;
y:OUT STD_LOGIC);
END or1;
ARCHITECTURE example1 OF or1 IS
BEGIN
y<=a OR b;
END example1;