LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY latch1 IS
PORT(d:IN STD_LOGIC;
ena:IN STD_LOGIC;
q:OUT STD_LOGIC);
END latch1;
ARCHITECTURE example4 OF latch1 IS
BEGIN
PROCESS(d,ena)
BEGIN
IF ena='1' THEN
q<=d;
END IF;
END PROCESS;
END example4;
锁存器
最新推荐文章于 2024-06-06 22:12:34 发布