#ifdef CYG_HAL_STARTUP_NAND // reset NAND mov r1, #NAND_CTL_BASE ldr r2, = 0xf830 // initial value str r2, [ r1, #oNFCONF] ldr r2, [ r1, #oNFCONF] bic r2, r2, #0x800 // enable chip str r2, [ r1, #oNFCONF] mov r2, #0xff // RESET command strb r2, [ r1, #oNFCMD] mov r3, #0 // wait 1: add r3, r3, #0x1 cmp r3, #0xa blt 1b 2: ldr r2, [ r1, #oNFSTAT] // wait ready tst r2, #0x1 beq 2b ldr r2, [ r1, #oNFCONF] orr r2, r2, #0x800 // disable chip str r2, [ r1, #oNFCONF] // copy redboot to RAM // Set up a stack [ for calling C code] ldr r1, = __startup_stack ldr r2, = LEO2410_SDRAM_PHYS_BASE orr sp, r1, r2 ldr r2, = __rom_data_end ldr r0, = __exception_handlers sub r2, r2, r0 ldr r0, = __exception_handlers ldr r1, = LEO2410_SDRAM_PHYS_BASE orr r0, r0, r1 mov r1, # 0x0 bl nand_read_ll teq r0, #0x0 beq ok_nand_read 1: b 1b // infinite loop ok_nand_read: // verify mov r0, #0 ldr r1, = __exception_handlers ldr r2, = LEO2410_SDRAM_PHYS_BASE orr r1, r1, r2 mov r2, #0x400 // 4 bytes * 1024 = 4K- bytes go_next: ldr r3, [ r0] , #4 ldr r4, [ r1] , #4 teq r3, r4 bne notmatch subs r2, r2, #4 beq done_nand_read bne go_next notmatch: 1: b 1b done_nand_read: // jump to ram ldr r1, = on_the_ram ldr r2, = LEO2410_SDRAM_PHYS_BASE add pc, r1, r2 nop nop 1: b 1b // infinite loop on_the_ram: #endif /* CYG_HAL_STARTUP_NAND * / |