一、异步复位加法计数器
代码:
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity CNT10 is port( CLK,RST,EN: in std_logic; DOUT : out std_logic_vector (3 downto 0); COUT : OUT std_logic ); end CNT10; architecture behav of CNT10 is begin process(CLK,RST,EN) variable Q : std_logic_vector (3 downto 0); begin if RST = '1' then Q := (others => '0'); elsif CLK '