module data_clock
(
input i_sys_clk,
input i_sys_rstn,
output [3:0] shi,
output [5:0]fen,
output [5:0] miao
);
//miao cnt;
reg [5:0] miao_cnt;
always@(posedge i_sys_clk or negedge i_sys_rstn)begin
if(i_sys_rstn==1'b0)begin
miao_cnt <= 6'd0;
end
else if(miao_cnt==6'd60)begin
miao_cnt <= 6'd0;
end
else begin
miao_cnt <= miao_cnt + 1'b1;
end
end
//fen cnt;
reg [5:0] fen_cnt;
al
(
input i_sys_clk,
input i_sys_rstn,
output [3:0] shi,
output [5:0]fen,
output [5:0] miao
);
//miao cnt;
reg [5:0] miao_cnt;
always@(posedge i_sys_clk or negedge i_sys_rstn)begin
if(i_sys_rstn==1'b0)begin
miao_cnt <= 6'd0;
end
else if(miao_cnt==6'd60)begin
miao_cnt <= 6'd0;
end
else begin
miao_cnt <= miao_cnt + 1'b1;
end
end
//fen cnt;
reg [5:0] fen_cnt;
al