https://accellera.org/downloads/standards/systemrdl
SystemRDL 2.0
SystemRDL Register Description Language
一次定义,多种HDL语言场合使用
事先有哪些寄存器需要定义,规划完毕,然后用SystemRDL来做描述,然后可以编译成多种硬件描述语言的版本,保持不同语言间寄存器的一致性。
https://github.com/SystemRDL/systemrdl-compiler
https://github.com/zhajio1988/Open_RegModel
https://accellera.org
Latest Downloads
A Guide to SystemC
https://www.doulos.com/knowhow/systemc/
https://ieeexplore.ieee.org/document/1617814
1666-2005 - IEEE Standard SystemC(R) Language Reference Manual
https://ieeexplore.ieee.org/document/8299595
1800-2017 - IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language
https://ieeexplore.ieee.org/document/1620780
1364-2005 - IEEE Standard for Verilog Hardware Description Language
https://ieeexplore.ieee.org/document/4772740
1076-2008 - IEEE Standard VHDL Language Reference Manual