(UVM验证学习7) ahb master验证组件实现学习

实现一个ahb master端的uvm验证组件

定义uvm_sequence_item

class ahb_trans extends uvm_sequence_item;

	rand bit [`MAX_DATA_WIDTH-1 : 0] data[];
	rand bit [`MAX_ADDR_WIDTH-1 : 0] addr = 0;

	rand burst_size_enum burst_size = BURST_SIZE_8BIT;
	rand burst_type_enum burst_type = SINGLE;
	rand xact_type_enum xact_type = IDLE_XACT;
	rand response_type_enum = response_type = OKAY;

	trans_type_enum trans_type;
	response_type_enum all_beat_response[];
	int current_data_beat_num;
	status_enum status = INITIAL;
	rand bit idle_xact_hwrite = 1;

endclass

定义sequencer

// 只需要包含config和vif
ahb_agent_configuration cfg;
virtual ahb_if vif;

定义driver

首先定义基类driver,可以被master端和slave端的driver继承,包含一些通用方法

class ahb_driver #(type REQ = ahb_trans, type RSP=REQ) extends uvm_driver #(REQ, RSP);
	ahb_agent_configuration cfg;
	virtual ahb_if vif;

	task run_phase(uvm_phase phase);
		super.run(phase);
		fork
			get_and_drive();
			reset_listener();
		join
	endtask
	
	virtual task get_and_drive();
		forever begin
			seq_item_port.get_next_item(req);
	
			driver_transfer(req);
			void'($cast(rsp, req.clone()));
			rsp.set_sequencer_id(reg.get_sequence_id());
			rsp.set_transaction_id(reg.get_transaction_id());

			seq_item_port.item_done(rsp);
		end
	endtask

	virtual task driver_transfer(REQ t);
	endtask

	virtual task reset_listener();
	endtaskl

endclass

随后定义master的driver,主要是重载一些父类提出的虚方法
其中drive_transfer()支支持SINGLE传输，随后区分是读操作还是写操作，具体的读写需要按照时序要求将数据分周期放置到总线上并记录相关信息。具体内容参考do_read(), do_write().

ahb_master_driver extends ahb_driver;

	virtual task