Quartus II 错误

1、  assign语句放在always中了；

//Error (10137): Verilog HDL Procedural Assignment error at bcd_code.v(39): object "qout" on left-hand side of assignment must have a variable data type

2、  ·timescale用的是进制符号，应该是键盘左上角；

//Error (10170): Verilog HDL syntax error at bcd_code_tb.v(1) near text: '. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Altera Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
3、# ** Error (suppressible): D:/altera/bcd_code/tb/bcd_code_tb.v(14): (vlog-2388) 'clk' already declared in this scope (bcd_code_tb).

故障代码
bcd_code   bcd_code0(
                            .clk(clk),
                            .cin(cin),
                            .rst(rst),
                            .Cout(Cout),
                            .qout(qout)
                            );
reg clk;
reg cin;
reg rst;

wire Cout;
wire [3:0]qout;

出现这个错误的原因：bcd_code0模块例化出现在了reg     clk;之前，也就是例化模块里面的变量要先申明，将clk的申明写到test例化之前错误就解决了。