奇偶检测
奇检测:输入的数据里有奇数个 1 就输出 1;
偶检测:输入的数据里有偶数个 1 就输出 1;
`timescale 1ns/1ns
module odd_sel(
input [31:0] bus,
input sel,
input clk, output check
);
reg check1;
wire sum;
assign sum = ^bus;
assign check = sel?(sum?1:0):(!sum?1:0);
endmodule
仿真波形
更换
assign check = sel?(sum?1:0):(!sum?1:0);
always@(negedge clk)
begin
case(sel)
0: if(!sum)
check1 <= 1;
else
check1 <= 0;
1: if(sum)
check1 <= 1;
else
check1 <= 0;
endcase
end
assign check = check1;
与 assign 比较输出会延时一个 clk