Chapter 67Low Power Serial Peripheral Interface (LPSPI) _3

目录

67.3 Functional description

67.3.1 Master mode

67.3.1.1 Transmit and Command FIFO commands

67.3.1.2 Receive FIFO and Data Match

67.3.1.3 Timing parameters

67.3.1.4 Pin configuration 端子配置

67.3.1.5 Clock loopback

67.3.2 Slave mode

67.3.2.1 Transmit and Command FIFO commands

67.3.2.2 Receive FIFO and data match

67.3.2.3 Partial Received Word

67.3.2.4 Clocked interface  （时钟接口）

67.3.3 Low power modes  √

67.3.4 Debug mode           √

67.3.5 Interrupts and DMA Requests

67.3.6 Clocks

67.3.7 Resets √

67.3.8 Peripheral Triggers   待解析。。。

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67.3 Functional description

67.3.1 Master mode

67.3.1.1 Transmit and Command FIFO commands

The transmit and command FIFO is a combined FIFO that includes both transmit data words and command words.

• Transmit data words are stored to the transmit/command FIFO, by writing the Transmit Data (TDR).

• Command words are stored to the transmit/command FIFO, by writing the Transmit Command (TCR).

When a command word is at the top of the transmit/command FIFO, the actions that can occur depend upon whether the LPSPI module is either busy or between frames. 

67.3.1.2 Receive FIFO and Data Match

67.3.1.3 Timing parameters

67.3.1.4 Pin configuration 端子配置

67.3.1.5 Clock loopback

67.3.2 Slave mode

LPSPI slave mode:
• Uses the same shift register and logic that master mode uses
• Does not use the Clock Configuration Register (CCR)
• During SPI bus transfers, requires that the Transmit Command (TCR) register remain static (unchanging)

67.3.2.1 Transmit and Command FIFO commands

67.3.2.2 Receive FIFO and data match

67.3.2.3 Partial Received Word

67.3.2.4 Clocked interface  （时钟接口）

The LPSPI module supports interfacing to external masters that provide only clock and data pins (PCS is not required).

从模式，只对外部主设备，提供数据和时钟3根线，（不需要PCS）

This interface requires:
• 使用时钟相位TCR[CPHA]=1（数据在SCK的前沿发生变化，在后沿捕获）

• Configuring the PCS input to be always asserted (CFGR1[PCSPOLn] = 1). For example, to configure PCS[0] to be always asserted, set PCSPOL[0] = 1, and do not configure PCS[0] in the pin muxing. The chip-level drives PCS to a certain value(ideally 1), CFGR1[PCSPOLn] could be used to invert that value.

• Setting CFGR1[AUTOPCS] = 1 (Automatic PCS generation is enabled).

When CFGR1[AUTOPCS] = 1, a minimum of 4 LPSPI functional clock cycles (divided by PRESCALE configuration) is required between the last SCK edge of one word and
the first SCK edge of the next word.

67.3.3 Low power modes

67.3.4 Debug mode

67.3.5 Interrupts and DMA Requests

The next table lists the slave mode sources (status flags) that can generate LPSPI interrupts and LPSPI slave transmit/receive DMA requests.

从模式下的中断

FCF
TCF	传输完成完成flag	Transfer is complete, PCS has negated, and the transmit/command FIFO is empty
TEF	传输错误

67.3.6 Clocks

Table 373. LPSPI Clocks

LPSPI Functional clock	• The LPSPI functional clock is asynchronous to the bus clock. 功能时钟对总线时钟是异步的； • If the LPSPI functional clock remains enabled in low power modes, then LPSPI can perform SPI bus transfers and low power wakeups, in both master and slave modes. 在low power模式，功能时钟保持使能；LPSPI可以主和从模式下支持SPI总线传输和唤醒； • The LPSPI divides the functional clock by a prescaler; the resulting frequency must be at least 2 times faster than the SPI external clock frequency (SCK).
External clock （SCK）	• The LPSPI shift register is clocked directly by the SCK clock. LPSPI移位寄存器由SCK时钟直接计时。 • How the SCK clock is generated or supplied depends upon the mode (master or slave): — In master mode: the SCK clock is generated internally. — In slave mode: the SCK clock is supplied externally.
Bus clock	The bus clock is only used for bus accesses to the LPSPI control and configuration registers. The bus clock frequency must be high enough to support the data bandwidth requirements of the LPSPI registers, including the FIFOs.

67.3.7 Resets

For chip-specific clocking information, see the Clocking chapter.

67.3.7 Resets

67.3.8 Peripheral Triggers   待解析。。。