Chapter 67Low Power Serial Peripheral Interface (LPSPI)_2

 67.2 Overview

废话，

LPSPI是有效的SPI总线接口，可以做主或从。spi是嵌入式系统的同步通讯接口，在印刷电路板上，典型的应用于微处理器与外设之间的短距通讯。

LPSPI is a low-power Serial Peripheral Interface (SPI) module that supports an efficient interface to an SPI bus, either as a master and/or as a slave. The SPI bus is a synchronous serial communication interface used in embedded systems, typically to perform short distance communications between microcontrollers and peripheral devices, on printed circuit boards. Typical applications include interfacing to Secure Digital cards and LCD displays.

67.2.1 Block diagram

 重要

图里的文字重要（这个图默认是salave模式）

Clock Domains：时钟域；

                数据移位器：从模式，使用外部时钟（sck）；

External Spi Interface:外部SPI接口

HREQ 端子（Host request 端子），

           Host不是master 主机的意思，而是作为本次通讯的发起者意思；本次通讯的发起者，可以是master 主机，也可以是slave从机；

          作slave模式和master模式都可以使用，作为请求本次SPI通讯开始（也可以不使用）；

         具体逻辑时序如下:

        Host Request pin is selected when CFGR0[HREN] =1 and CFGR0[HRSEL] = 0

        • Input in either slave mode or when used as master Host Request

        • Output in either master mode or when used as slave Host Request

PCS    端子 （Peripheral chip select）外设选择，片选；(从模式输入，主模式输出)

          master模式下，PCS和SCK配合，对从设备输出时序和片选；

SIN,SOUT端子：数据线；

SCK 端子         ：时钟线；

67.2.2 Features 

总结：DMA，时钟相位极性配置，主支持8路片选，支持从模式，FIFO为4WORD,灵活定时；

LPSPI supports:

• Uses little CPU overhead, with DMA offloading of FIFO register accesses

FIFO寄存器访问的转移用DMA
• Supports DMA accesses and generates a DMA request

• Word size of 32 bits

• Configurable clock polarity and clock phase

    配置时钟相位极性
• Master operation supporting up to 8 peripheral chip selects

主模式支持8路外设片选
• Slave operation

从模式
• Command/transmit FIFO of 4 words

支持，传输4个word（4*32bit，16字节）

• Receive FIFO of 4 words

支持，接收4个word（4*32bit，16字节）

• Flexible timing parameters in Master mode, including SCK frequency, duty cycle, and delays between PCS and SCK edges

master模式下支持，灵活的定时；sck频率，时钟占空比，pcs与sck延后时长；
• Continuous transfer option to keep the PCS asserted across multiple frames

连续传输功能，是PCS在多个帧传输中有效；
• Full duplex transfers supporting 1-bit transmit and receive on each clock edge

全双工传输支持：在每个时钟边缘进行1位发送和接收（一般用这个模式）
• Half duplex transfers supporting 1-bit transmit or receive on each clock edge

办双工传输支持：在每个时钟边缘进行1位发送或接收

• Half duplex transfers supporting 2-bit transmit or receive on each clock edge
• Half duplex transfers supporting 4-bit transmit or receive on each clock edge
• Half duplex transfers supporting 8-bit transmit or receive on each clock edge

• Host request can be used to control the start of a SPI bus transfer

主机请求可用于控制SPI总线传输的启动

• Receive data match logic supporting wakeup on data match

接收数据匹配逻辑，支持数据匹配唤醒

问题：

1.HREQ是什么？和trigger区别？

2.