V5 IBIS model of SSTL DCI
- Howdy all.
- I havn't been able to locate infomation on this, so I apologize if this has been discussed before.
- I am doing some signal integrity simulations between a V5 LX110T and a DDR2 memory array. The data lines (DQ) are using SSTL18_II_DCI as the IO standard. The IBIS model that is generated from ISE 9.2.02, however, creates a model of sstl18_ii_dci_o, which is setup for output only. The raw Virtex5 model that is downloaded from Xilinx has a bi-directional SSTL18_II_DCI model, but it is not added to the generated one. So my first question would be: How do I get the model to generate correctly?
- My second question(s) involves how the model handles DCI. As an output, the model does appear to be properly applying the series resistor for DCI. However, as an input, how does the model handle the Thevenin termination? In design, this termination is governed by Vrp, Vrn, and whatever voltages they are tied too. None of this info is entered into ISE, nor the model. So how does the model handle this termination? How can I change the parameters of it? And is there anywhere in the model that I can see how the termination created?
- Thanks for the help
- --Dominic
- Dominic,
- You can copy all of the IBIS models (Lines 450 through 100707 in the 8/10/07 version) from the general Virtex5 IBIS model into the custom IBIS model generated by ISE. Then in the Pin section change SSTL18_II_DCI_O to SSTL18_II_DCI. To avoid conflicts between models with the same name, I deleted all of the IBIS models in the custom ISE model first.
- I also suggest that you download the .pkg model for your package and include it in your simulation. You will have to add the Package Model definition to the IBIS model:
- [Package]
- | For Package Type ff1738
- | variable typ min max
- R_pkg 392.05m 18.4m 859.03m
- L_pkg 5.11nH 1.32nH 9.61nH
- C_pkg 3.15pF 1.11pF 5.72pF
- |
- [Package Model] ff1738_5vlx330t
- |
- |
- [Pin] signal_name model_name R_pin L_pin C_pin
- |
- AM31 gbm1_mem2_addr<0> SSTL18_I_I
- Please let me know if you found the answer to the second part regarding how the DCI is modeled.
- Steve.
- I am using the LVDCI IO standard using a virtex 4 FX100 FPGA. I can define a a signal as follows:
- NET "a" LOC = "l25" | IOSTANDARD = LVDCI_33;
- However, i know that the value that the DCI uses is determined by an external resistor. In this case i have a 100 ohm resistor attached to pin G28 of the virtex 4 FPGA. Do i need to add any lines to the UCF file to tell the FPGA to look at this pin to find the DCI value, or does it automatically do this since i am using a DCI standard?
- cheers,
- Fraser
- p.s the pins are all on the same bank
- Hi Fraser,
- If the bank has DCI io standards then it will automatically know to look for the DCI voltage reference resistor on the VRN and VRP pins for the bank. So, you don't need to specify anything else in the UCF.
- D