实验六encode_8_3

library ieee;  
use ieee.std_logic_1164.all; 
use ieee.numeric_std.all;
  
entity encode_8_3 is  
  
port   
  (  
     en:in std_logic;
     i: in std_logic_vector(7 downto 0);  
     
      d: out std_logic_vector(2 downto 0);
     nul,inv:out std_logic
);  
end entity encode_8_3;  
  
architecture rtl of  encode_8_3 is  

begin   
  
     process(en,i)is
       begin

       if(en='0')then
          d <="ZZZ";nul<='Z';inv<='Z';


       else 
          case i is

            when "01111111" => d<="000";nul<='0';inv<='0';
            when "10111111" => d<="001";nul<='0';inv<='0';
            when "11011111" => d<="010";nul<='0';inv<='0';		 
            when "11101111" => d<="011";nul<='0';inv<='0';
            when "11110111" => d<="100";nul<='0';inv<='0';
            when "11111011" => d<="101";nul<='0';inv<='0';
            when "11111101" => d<="110";nul<='0';inv<='0';
            when "11111110" => d<="111";nul<='0';inv<='0';
            when "11111111" => d<="000";nul<='1';inv<='0';
            
            	
            when others =>d<="000";nul<='0';inv<='1';


          end case;
       end if;
      end process;
   end architecture rtl;