8-3优先编码器 Verilog-modelsim

#8-3优先编码器 Verilog-modelsim

##tb.v (tb)

`timescale 1ns/1ns	
module tb;          
   reg [7:0] din;
  wire [2:0] dout;   

  initial begin
  	               din = 8'b00000000 ;
      forever #5   din = din+1;	
  end
				 

YOUXIAN83 u_YOUXIAN83
    (  .din       (din  ),
       .dout      (dout  )
    );									
  															
endmodule												

##test.do (sim)

# step 1
vlib work

# step 2
vlog ../rtl/83youxian.v
vlog ../tb/tb.v

#step 3
vsim tb

##83youxian.v (rtl)

module YOUXIAN83 ( din,dout );
 input  [7:0]  din;
 output [0:2] dout;
    reg [2:0] dout;
always @( * )
  begin
	       if (din==8'b???????0) dout=3'b000;
	  else if (din==8'b??????01) dout=3'b100;
	  else if (din==8'b?????011) dout=3'b010;
   	else if (din==8'b????0111) dout=3'b110;
   	else if (din==8'b???01111) dout=3'b001;
   	else if (din==8'b??011111) dout=3'b101;
	  else if (din==8'b?0111111) dout=3'b011;
	  else if (din==8'b01111111) dout=3'b111;
                          else dout=3'b000;
  end
endmodule