** Error: (vsim-3170) Could not find ‘work.mux31a_vlg_vec_tst’.
全程编译只有几个警告,没有错误,搞不懂是哪里的问题,在线等,很急,有没有懂得大佬指点一下
下面是我的代码
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MUX31A IS
PORT ( a1,a2,a3,s1,s0 : IN STD_LOGIC ;
outy : OUT STD_LOGIC );
END ENTITY MUX31A;
ARCHITECTURE bhv OF MUX31A IS
SIGNAL tmp : STD_LOGIC;
COMPONENT MUX21A
PORT ( a,b,s : IN STD_LOGIC;
y : OUT STD_LOGIC);
END COMPONENT;
BEGIN
u1: MUX21A PORT MAP( a=>a2 , b=>a3 , s=>s0 , y=>tmp );
u2: MUX21A PORT MAP( a=>a1 , b=>tmp , s=>s1 , y=>outy );
END ARCHITECTURE bhv;
工作库我直接建立在桌面上了