【AUTOSAR】BMS开发实际项目讲解（六）----BMS软件架构设计

1. 1. Terms and Abbreviation

No.	Terms/Abbreviation	Explanation
1	SRS	Software Requirement Specification
2	TSR	Technical Safety Requirements
3	FSR	Functional Safety Requirements
4	IC	Integrated Circuit
5	HIS	Hardware Software Interface
6	ID	Identification
7	FS	Function Safety
8	NFS	Non-Function Safety
9	SA	Software Architecture
10	DET	Default Error Tracer (AUTOSAR) / Diagnostic Exception Tracer (This document)
11	NM	CAN Network Management
12
13

表1

1. 1. References
      1. Project Reference Documents

No.	Name	Version	Date
1	DHEV-FS-T6-61 SW Safety Requirements Specification	1.2	2019/9/15
2	DHEV-FS-T4-62 System Design Specification	2.0	2019/1/5
3	DHEV-FS-T5-32 HW-SW Interface Specification	02

表2

1. 1. 1. Outside Reference Documents

No.	Name	Version	Date
1	ISO 26262-6 Road vehicles — Functional safety — Part 6: Product development at the software level	Second edition	2018-12
2
3

表3

1. Assumptions and Constrains

主 CPU: Infineon TC275TP

硬件约束：PFLASH: 4M Byte、Data Flash: 384K Byte、DSPR: 120K Byte、PSPR: 20K Byte

内存消耗：整体使用率≤ 80%，对于栈：正常运行≤ 70%, 压力测试≤85%

CPU负载约束：正常运行≤ 70%, 压力测试≤ 85%

软件运行环境约束：运行在RTOS环境下，使用符合AUTOSAR标准的操作系统RTA-OS

时间约束：在RTOS环境下，各任务执行的超时时间误差≤ 5%，功能安全需求相关任务执行的时间误差≤ 2%

从 CPU: Freescale MM9Z1_638

硬件约束：Flash: 128 kByte、RAM: 8.0 kByte、EEPROM: 4.0 kByte

内存消耗：整体使用率≤ 80%，对于栈：正常运行≤ 70%, 压力测试≤85%

CPU负载约束：正常运行≤ 70%, 压力测试≤ 85%

软件运行环境约束：无RTOS的前后台运行环境

时间约束：在前后台运行环境下，各周期性调用的函数执行的超时时间误差≤ 5%，功能安全需求相关周期性调用的函数执行的时间误差≤ 2%

1. Compile Environment

Master CPU: TASKING VX-toolset for TriCore v4.2r2

Slave CPU: CodeWarrior Development Studio for Microcontrollers v10.7

1. Software Architecture Design
   1. Software Architecture Overview
      1. Software Architecture Diagram (Slave CPU)

 

1. 1. 1. Layer & Module definition (Slave CPU)

Module	Description	ASIL	Comments
ADC	Analog to Digital converter	ASIL A
CAN	Controller Area Network	ASIL A
Interrupt module	/	ASIL A
Period interrupt	/	ASIL A
COP Watchdog	/	ASIL A
System Clock	/	ASIL A