大二做的一个计算机组成原理课程设计,用verilog实现一个五级流水线的CPU。
主要实现了加减、比较、左移右移、条件跳转等的精简指令集。
`timescale 1ns / 1ps
`define idle 1'b0
`define exec 1'b1
//Data Transfer & Arithmetic
`define NOP 5'b00000
`define HALT 5'b00001
`define LOAD 5'b00010
`define STORE 5'b00011
`define LDIH 5'b10000
`define ADD 5'b01000
`define ADDI 5'b01001
`define ADDC 5'b10001
`define SUB 5'b01010
`define SUBI 5'b01011
`define SUBC 5'b10010
`define CMP 5'b01100
//Logical/Shift
`define AND 5'b01101
`define OR 5'b01110
`define XOR 5'b01111
`define SLL 5'b00100
`define SRL 5'b00110
`define SLA 5'b00101
`define SRA 5'b00111
//Control
`define JUMP 5'b11000
`define JMPR 5'b11001
`define BZ 5'b11010
`define BNZ 5'b11011
`define BN 5'b11100
`define BNN 5'b11101
`define BC 5'b11110
`define BNC 5'b11111
//************************************************//
//* You need to complete the design below *//
//* by yourself according to your operation set *//
//************************************************//
module CPU(
input [15:0]i_datain,
input [15:0]d_datain,
input clock,
input reset,
input enable,
input start,
//input [3:0]select_y,
//output reg [15:0]y,
output [7:0]i_addr,
output [7:0]d_addr,
output [15:0]d_dataout,
output d_we
);
reg [15:0]gr[7:0];
reg state;
reg next_state;
reg [7:0]pc;
reg [15:0]id_ir;
reg [15:0]ex_ir;
reg [15:0]mem_ir;
reg [15:0]wb_ir;
reg [15:0]reg_A;
reg [15:0]reg_B;
reg [15:0]reg_C;
reg [15:0]reg_C1;
reg [15:0]smdr;
reg [15:0]smdr1;
wire [15:0]ALUo;
reg nf,zf,dw;
wire cf;
assign i_addr = pc;
assign d_addr = reg_C[7:0];
assign d_we = dw;
assign d_dataout = smdr1;
//************* CPU control *************//
always @(posedge clock)
begin
if (!reset)