library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity adder_4 is
port(a: in std_logic-vector(3 downto 0);
b: in std-logic-vector(3 downto 0);
co:out std-logic;
sum: out std-logic-vector(3 downto 0)
);
end adder-4;
architecture Behavioral of adder-4 is
begin
process(a,b)
variable a1,b1,c1: std-logic-vector(4 downto 0);
begin
a1:=‘0’& a;
b1:=‘0’& b;
c1:=a1+b1;
sum<=c1(3 downto 0);
end process;
end Behavioral;
VHDL四位加法器设计
最新推荐文章于 2024-05-27 19:33:01 发布