SMP support in JOS

Multiprocessor Support

We are going to make JOS support "symmetric multiprocessing" (SMP), amultiprocessor model in which all CPUs have equivalent access tosystem resources such as memory and I/O buses. While all CPUsare functionally identical in SMP, during the boot process theycan be classified into two types: the bootstrap processor (BSP) isresponsible for initializing the system and for booting the operatingsystem; and the application processors (APs) are activated by the BSPonly after the operating system is up and running. Which processor isthe BSP is determined by the hardware and the BIOS. Up to this point,all your existing JOS code has been running on the BSP.

1. APIC

The APICs help achieve the goal of scalability by doing the following:
•  Off-loading interrupt-related traffic from the memory bus, making the memory bus more
available for processor use.
•  Helping processors share the interrupt processing load with other processors.

In an SMP system, each CPU has an accompanying local APIC (LAPIC) unit.The LAPIC units are responsible for delivering interrupts throughoutthe system. The LAPIC also provides its connected CPU with a uniqueidentifier. Usually LAPIC at least includes these functions:

• Reading the LAPIC identifier (APIC ID) to tell which CPU our code iscurrently running on.
• Sending the STARTUP interprocessor interrupt (IPI) fromthe BSP to the APs to bring up other CPUs.
• In part C, we program LAPIC's built-in timer to trigger clockinterrupts to support preemptive multitasking.

Memory mapping in APIC

In a compliant system, all APICs must be implemented as memory-mapped I/O devices. APIC
base addresses are at the top of the memory address space. All APIC local units are mapped to the
same addresses, which are not shared. Each processor accesses its local APIC via these memory
addresses. The default base address for the local APICs is 0FEE0_0000h.
Unlike the local APICs, the I/O APICs are mapped to give shared access from all processors,
providing full symmetric I/O access. The default base address for the first I/O APIC is
0FEC0_0000h. Subsequent I/O APIC addresses are assigned in 4K increments. For example, the
second I/O APIC is at 0FEC0_1000h.
Non-default APIC base addresses can be used if the MP configuration table is provided. (Refer to
Chapter 4.) However, the local APIC base address must be aligned on a 4K boundary, and the I/O
APIC base address must be aligned on a 1K boundary.

2.  System Memory

A system that complies with the MP specification uses the standard AT memory architecture. All
memory is allocated for system memory with the exception of addresses 0A_0000h through
0F_FFFFh and 0FFFE_0000h through 0FFFF_FFFFh, which are reserved for I/O devices and the
BIOS.
Compared to a uniprocessor system, a symmetric multiprocessor system imposes a high demand
for memory bus bandwidth. The demand is proportional to the number of processors on the
memory bus. To reduce memory bus bandwidth limitations, an implementation of this
specification should use a secondary cache that has high-performance features, such as a write-back
update policy and a snooping cache-consistency protocol. A secondary cache can push the
scalability limit upward by reducing bus traffic and increasing bus bandwidth.

3. BIOS

A standard uniprocessor BIOS performs the following
functions:
•Tests system components.
•Builds configuration tables to be used by the operating system.
•Initializes the processor and the rest of the system to a known state.
•Provides run-time device-oriented services.
For a multiprocessor system, the BIOS may perform the following additional functions:
•Pass configuration information to the operating system that identifies all processors and other
multiprocessing components of the system.
•Initialize all processors and the rest of the multiprocessing components to a known state.

4. MP Configure Data Structure ( Configure table & MP Floating Pointer Structure)

5. Operating System Programming guidelines

1. Operating-system boot-up.
2. Self configuration.
3. Interrupt mode initialization.
4. Application processor startup.
5. Application processor shutdown.
6. Dynamic interrupt masking.
7. Support for unequal processors.