备战2021数字IC暑期实习&秋招-Verilog手撕代码篇【1】

Problem1: 序列检测

Description

检测序列“1010110”，检测到该序列时输出高脉冲

1. 使用Moore型状态机和Mealy型状态机实现序列的重复检测和非重复检测
2. 使用移位寄存器实现，重复检测和不重复检测

系统架构（输入输出）：

关于moore型和Mealy型状态机结构图如下：

Solution1：FSM

1、序列1010110的非重复检测

Moore型状态机和Mealy型状态机状态转移图如下：

画出状态转移图后，自然的，代码也就出来了，这里采用三段式FSM，代码如下：

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2021/04/03 22:22:41
// Design Name: 
// Module Name: flow_check
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module flow_check(
    input           clk,
    input           rst_n,
    input           idata,
    output reg      valid 
);

    parameter           S0      =       8'b0000_0001;
    parameter           S1      =       8'b0000_0010;
    parameter           S2      =       8'b0000_0100;
    parameter           S3      =       8'b0000_1000;
    parameter           S4      =       8'b0001_0000;
    parameter           S5      =       8'b0010_0000;
    parameter           S6      =       8'b0100_0000;
    parameter           S7      =       8'b1000_0000;
    
    reg             [7:0]       c_state;
    reg             [7:0]       n_state;

    //从现态转移到次态
    always @ (posedge clk, negedge rst_n) begin
        if(rst_n == 1'b0) 
            c_state <= S0;
        else 
            c_state <= n_state;
    end

    //根据现态和输入决定次态输出
    always @ * begin
        case (c_state) 
            S0      :       begin
                if (idata == 1'b1)
                    n_state = S1;
                else 
                    n_state = S0;
            end
            S1      :       begin
                if (idata == 1'b1)
                    n_state = S1;
                else 
                    n_state = S2;
            end
            S2      :       begin
                if (idata == 1'b1)
                    n_state = S3;
                else 
                    n_state = S0;
            end
            S3      :       begin
                if (idata == 1'b1)
                    n_state = S1;
                else 
                    n_state = S4;
            end
            S4      :       begin
                if (idata == 1'b1)
                    n_state = S5;
                else 
                    n_state = S0;
            end
            S5      :       begin
                if (idata == 1'b1)
                    n_state = S6;
                else 
                    n_state = S4;
            end
            S6      :       begin
                if (idata == 1'b1)
                    n_state = S1;
                else 
                    n_state = S7;
            end
            S7      :       begin
                if (idata == 1'b1)
                    n_state = S1;
                else 
                    n_state = S0;
            end
            default: n_state = S0;
        endcase
    end

    //根据现态决定输出(Moore型FSM)
    always @ (posedge clk, negedge rst_n) begin
        if(rst_n == 1'b0) begin
           valid <= 1'b0; 
        end
        else if (c_state == S7)
            valid <= 1'b1;
        else 
            valid <= 1'b0;
    end
endmodule

tb如下：

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
/