SystemVerilog基础知识 1.new()和new[]

new()和new[]有什么区别???

systemverilog 语法中构造函数new有两种,new()和new[],二者的使用区别很大。

1.new[]

new[]的使用较为简单,一般用来开辟内存并初始化,常用于设置动态数组的大小。

如下例:

int a[];   //声明动态数组
initial begin
a = new[3];  //为动态数组分配3个元素
foreach (a[i]) a[i] = i;   //元素初始化
end

声明动态数组后,尚不知道数组内的元素个数,直到仿真时,才能确定动态元素个数,因此必须通过调用new[]函数分配空间,并确定数组中元素个数。

2.new()

new()用于在SV中OOP的构造函数,构造函数除了分配内存外,还初始化变量,创建对象开辟了新的内存空间,可以存放新的成员变量和方法,构建函数new()是系统预预定函数,不需要指定返回值,函数会隐式的返回例化后的对象指针,构建函数可以定义多个参数作为初始化时外部传入数值的手段。

class example1;//创建一个类
        logic[3:0] addr;
        logic[9:0] data;
        int dyn[];
        function new;
                addr = 8;
                data = 1;
        endfunction
        dyn = new[8];
        foreach (dyn[i]) dyn[i] = i;
endclass
example1 ex;   //声明一个句柄
ex = new();    //将句柄实例化

new()函数有三个作用:

  1. 例化对象,申请新的内存地址;
  2. 初始化变量,二值变量初始化为0,四值变量初始化为X;
  3. 返回句柄。
Transaction tr; //声明一个句柄
tr = new(); //创建对象
  • 0
    点赞
  • 11
    收藏
    觉得还不错? 一键收藏
  • 1
    评论
The Verilog language is a hardware description language that provides a means of specifying a digital system at a wide range of levels of abstraction. The language sup- ports the early conceptual stages of design with its behavioral level of abstraction, and the later implementation stages with its structural abstractions. The language includes hierarchical constructs, allowing the designer to control a description's complexity. Verilog was originally designed in the winter of 1983/84 as a proprietary verifica- tion/simulation product. Later, several other proprietary analysis tools were developed around the language, including a fault simulator and a timing analyzer. More recently, Verilog has also provided the input specification for logic and behavioral synthesis tools. The Verilog language has been instrumental in providing consistency across these tools. The language was originally standardized as IEEE standard #1364-1995. It has recently been revised and standardized as IEEE standard #1364-2001. This book presents this latest revision of the language, providing material for the beginning student and advanced user of the language. It is sometimes difficult to separate the language from the simulator tool because the dynamic aspects of the language are defined by the way the simulator works. Fur- ther, it is difficult to separate it from a synthesis tool because the semantics of the lan- guage become limited by what a synthesis tool allows in its input specification and produces as an implementation. Where possible, we have stayed away from simulator- and synthesis-specific details and concentrated on design specification. But, we have included enough information to be able to write working executable models. xvi The VerUog Hardware Description Language The book takes a tutorial approach to presenting the language. Indeed, we start with a tutorial introduction that presents, via examples, the major features of the lan- guage and the prevalent styles of describing systems. We follow this with a detailed presentation on using the language for synthesizing combinational and sequential sys- tems. We then continue with a more complete discussion of the language constructs. Our approach is to provide a means of learning by observing the examples and doing exercises. Numerous examples are provided to allow the reader to learn (and re- learn!) easily by example. It is strongly recommended that you try the exercises as early as possible with the aid of a Verilog simulator. The examples shown in the book are available in electronic form on the enclosed CD. Also included on the CD is a simulator. The simulator is limited in the size of description it will handle. The majority of the book assumes a knowledge of introductory logic design and sof~are programming. As such, the book is of use to practicing integrated circuit design engineers, and undergraduate and graduate electrical or computer engineering students. The tutorial introduction is organized in a manner appropriate for use with a course in introductory logic design. A separate appendix, keyed into the tutorial introduction, provides solved exercises that discuss common errors. The book has also been used for courses in introductory and upper level logic and integrated circuit design, computer architecture, and computer-aided design (CAD). It provides com- plete coverage of the language for design courses, and how a simulator works for CAD courses. For those familiar with the language, we provide a preface that covers most of the new additions to the 2001 language standard. The book is organized into eleven chapters and eight appendices. The first part of the book contains a tutorial introduction to the language which is followed by a chap- ter on its use for logic synthesis. The second part of the book, Chapters 3 through 6, provide a more rigorous presentation of the language's behavioral, hierarchical, and logic level modeling constructs. The third part of the book, Chapters 7 through 11, covers the more specialized topics of cycle-accurate modeling, timing and event driven simulation, user-defined primitives, and switch level modeling. Chapter 11 suggests two major Verilog projects for use in a university course. One appendix pro- vides tutorial discussion for beginning students. The others are reserved for the dryer topics typically found in a language manual; read those at your own risk.

“相关推荐”对你有帮助么?

  • 非常没帮助
  • 没帮助
  • 一般
  • 有帮助
  • 非常有帮助
提交
评论 1
添加红包

请填写红包祝福语或标题

红包个数最小为10个

红包金额最低5元

当前余额3.43前往充值 >
需支付:10.00
成就一亿技术人!
领取后你会自动成为博主和红包主的粉丝 规则
hope_wisdom
发出的红包
实付
使用余额支付
点击重新获取
扫码支付
钱包余额 0

抵扣说明:

1.余额是钱包充值的虚拟货币,按照1:1的比例进行支付金额的抵扣。
2.余额无法直接购买下载,可以购买VIP、付费专栏及课程。

余额充值