Verilog编程基础练习

一、3-8译码器仿真实验

1.logsim中仿真电路图

真值表

2.在quartus ii 13.1中用verilog编写3-译码器

verilog代码如下

 module decoder3_8
 (
 input wire in1 , //输入信号 in1
 input wire in2 , //输入信号 in2
 input wire in3 , //输入信号 in3
 output reg [7:0] out //输出信号 out
 );
 //out:根据 3 个输入信号选择输出对应的 8bit out 信号
 always@(*)
 //使用"{}"位拼接符将 3 个 1bit 数据按照顺序拼成一个 3bit 数据
 if({in1, in2, in3} == 3'b000)
 out = 8'b0000_0001;
 else if({in1, in2, in3} == 3'b001)
 out = 8'b0000_0010;
 else if({in1, in2, in3} == 3'b010)
 out = 8'b0000_0100;
 else if({in1, in2, in3} == 3'b011)
 out = 8'b0000_1000;
 else if({in1, in2, in3} == 3'b100)
 out = 8'b0001_0000;
 else if({in1, in2, in3} == 3'b101)
 out = 8'b0010_0000;
 else if({in1, in2, in3} == 3'b110)
 out = 8'b0100_0000;
else if({in1, in2, in3} == 3'b111)
 out = 8'b1000_0000;
 else
 out = 8'b0000_0001;
endmodule

RTL电路图

编写测试文件

`timescale 1ns/1ns
 module tb_decoder3_8();
 
 //reg define
 reg in1;
 reg in2;
 reg in3;
 
//wire define
 wire [7:0] out;

 //初始化输入信号
 initial begin
 in1 <= 1'b0;
 in2 <= 1'b0;
 in3 <= 1'b0;
 end
  //in1:产生输入随机数，模拟输入端 1 的输入情况
 always #10 in1 <= {$random} % 2; 
 
 //in2:产生输入随机数，模拟输入端 2 的输入情况
 always #10 in2 <= {$random} % 2; 
 
//in3:产生输入随机数，模拟输入端 3 的输入情况
 always #10 in3 <= {$random} % 2; 
 
 initial begin
 $timeformat(-9, 0, "ns", 6);
 $monitor("@time %t:in1=%b in2=%b in3=%b out=%b",$time,in1,in2,in3,out);
 end
//------------------------------------------------------------

//-------------decoder3_8_inst----------------
 decoder3_8 decoder3_8_ins
 (
 .in1(in1), //input in1
 .in2(in2), //input in2
 .in3(in3), //input in3
 
 .out(out) //output [7:0] out
 );

endmodule

二、全加器的仿真

1、一位全加器的仿真

logsim实现电路图

（1）verilog用门级电路描述

module adder_1bit(A,B,Cin,Sum,Cout);
input A,B,Cin;
output Sum,Cout;
wire t1,t2,t3;
xor U1(t1,A,B);
xor U2(Sum,t1,Cin);
and U3(t2,t1,Cin);
and U4(t3,A,B);
or  U5(Cout,t2,t3);
endmodule

RTL图

（2）用行为级方式实现

代码

module adder_1bit(
    input A,B,Cin,
	 output Sum,Cout);
	wire t1,t2,t3;
	assign Sum=A^B^Cin;
	assign t1=A&B,
	       t2=A&Cin,
			 t3=B&Cin;
	assign Cout=t1|t2|t3;
endmodule

RTL图

2.四位全加器

module FA(
       input x, y,cin,
		 output f, cout
);
       assign f=x^y^cin;
		 assign cout=(x & y)|(x & cin)|(y & cin);
endmodule
module adder_structural(
      input [3:0]x,y,
		input cin,
		output [3:0]f,
		output cout
);
		wire [4:0]c;
		assign c[0]=cin;
		FA fa0(x[0],y[0], c[0], f[0], c[1]);
		FA fa1(x[1],y[1], c[1], f[1], c[2]);
		FA fa2(x[2],y[2], c[2], f[2], c[3]);
		FA fa3(x[3],y[3], c[3], f[3], c[4]);
		assign cout = c[4];	
endmodule

3.Verilog的8位全加器模块设计

module eight_bit_adder(
    input [7:0] a,
    input [7:0] b,
    input cin,
    output [7:0] sum,
    output cout
);

wire [7:0] c;

full_adder fa0(a[0], b[0], cin, sum[0], c[0]);
full_adder fa1(a[1], b[1], c[0], sum[1], c[1]);
full_adder fa2(a[2], b[2], c[1], sum[2], c[2]);
full_adder fa3(a[3], b[3], c[2], sum[3], c[3]);
full_adder fa4(a[4], b[4], c[3], sum[4], c[4]);
full_adder fa5(a[5], b[5], c[4], sum[5], c[5]);
full_adder fa6(a[6], b[6], c[5], sum[6], c[6]);
full_adder fa7(a[7], b[7], c[6], sum[7], cout);

endmodule

module full_adder(
    input a,
    input b,
    input cin,
    output sum,
    output cout
);

assign sum = a ^ b ^ cin;
assign cout = (a & b) | (a & cin) | (b & cin);

endmodule