verilog语言设计分频器

`timescale 1ns/100ps

module fdtop;

reg RESET;

reg F10M=1'b0;

reg F500K=1'b0;

integer j=1;

 initial

 begin

  RESET<=1; 

 end

always #50 F10M = ~F10M;

   always @(posedge F10M)

   begin

     if(!RESET)          //??????

       begin

         F500K <= 0;

         j <= 0;

      end

     else 

       begin

         j <= j+1;