Platform: RK3399
OS: Android 7.1
Kernel: v4.4.83
需求:
默认codec的clock source是从I2S1的mclk获取,由于I2S0和I2S1的mclk是共用同一个,
而且同一时刻只有一个I2S模块才能使用,而I2S0需要接麦克阵列,因此I2S1接的RT5640 Codec的时钟源改从BCLK1来获取。
信号源选择方法:
参考RT5640 codec的数据手册中的图,clock source可以从MCLK也可以从PLL获取。
原理图:
5640和cpu的接法如下:
修改:
移除之前对I2S1修改的patch以及添加对5640 clock source的控制。
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-vop-clk-set.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-vop-clk-set.dtsi
index 8a98bbc..0546ed2 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-vop-clk-set.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-vop-clk-set.dtsi
@@ -89,12 +89,12 @@
assigned-clock-parents = <&cru PLL_GPLL>;
};
-/* Kris,180906, Fix playback noise issue.
+
&i2s1 {
assigned-clocks = <&cru SCLK_I2S1_DIV>;
assigned-clock-parents = <&cru PLL_GPLL>;
};
-*/
+
&i2s2 {
assigned-clocks = <&cru SCLK_I2S2_DIV>;
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 5bf6cb9..109d8ce 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1693,9 +1693,6 @@
dma-names = "tx", "rx";
clock-names = "i2s_clk", "i2s_hclk";
clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
- //Kris,180706, porting rt5640 on i2s1.
- assigned-clocks = <&cru SCLK_I2S_8CH>;
- assigned-clock-parents = <&cru SCLK_I2S1_8CH>;
pinctrl-names = "default";
pinctrl-0 = <&i2s1_2ch_bus>;
power-domains = <&power RK3399_PD_SDIOAUDIO>;
diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
index e2d872f..cd7b268 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -711,9 +711,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
&rk3399_i2s2_fracmux),
GATE(SCLK_I2S2_8CH, "clk_i2s2", "clk_i2s2_mux", CLK_SET_RATE_PARENT,
RK3399_CLKGATE_CON(8), 11, GFLAGS),
- //Kris,180706, porting rt5640 on i2s1.
- //MUX(0,