RT1020 lpspi 引脚配置

1.配置lpspi 引脚

8.1 Chip-specific Boot Information

This device has various peripherals supported by the ROM bootloader.

LPSPI1_SCK 配置为例

由上表可知 LPSPI1_SCK 连接到 GPIO_AD_B0_10

SW_MUX_CTL_PAD_GPIO_AD_B0_10

管脚复用寄存器 (IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_10) 

 

SW_PAD_CTL_PAD_GPIO_AD_B0_10

管脚控制寄存器 (IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_10) 

 

LPSPI1_SDI_SELECT_INPUT

DAISY Register (IOMUXC_LPSPI1_SDI_SELECT_INPUT) 

对于选择输入引脚还需要配置 DAISY 寄存器

/* LPSPI1_SCK*/
IOMUXC->SW_MUX_CTL_PAD[SW_MUX_CTL_PAD_LPSPI1_SCK_IDX] = LPSPI1_MUX_VAL;//引脚IOMUX 复用模式
IOMUXC->SW_PAD_CTL_PAD[SW_PAD_CTL_PAD_LPSPI1_SCK_IDX] = LPSPI_SW_PAD_CTL_VAL;//引脚PAD 属性配置

/* LPSPI1_SIN*/
IOMUXC->SW_MUX_CTL_PAD[SW_MUX_CTL_PAD_LPSPI1_SIN_IDX] = LPSPI1_MUX_VAL;
IOMUXC->SW_PAD_CTL_PAD[SW_PAD_CTL_PAD_LPSPI1_SIN_IDX] = LPSPI_SW_PAD_CTL_VAL;
/* For input pin, we must set corresponding SELECT_INPUT register */
//Selecting Pad: GPIO_AD_B0_13 for Mode: ALT1
IOMUXC->SELECT_INPUT[SELECT_INPUT_LPSPI1_SDI_IDX] = LPSPI1_SDI_SELECT_INPUT_VAL;

/* LPSPI1_SOUT*/
IOMUXC->SW_MUX_CTL_PAD[SW_MUX_CTL_PAD_LPSPI1_SOUT_IDX] = LPSPI1_MUX_VAL;
IOMUXC->SW_PAD_CTL_PAD[SW_PAD_CTL_PAD_LPSPI1_SOUT_IDX] = LPSPI_SW_PAD_CTL_VAL;

/* LPSPI1_PCS */
/* Note: So far we cannot do separated send and recive operation in one active pcs period in LPSPI driver
 *  To achieve this goal, we should config PCSx pin as GPIO and control it manually. */
IOMUXC->SW_MUX_CTL_PAD[SW_MUX_CTL_PAD_LPSPI1_PCS0_IDX] = GPIO_MUX_VAL;
IOMUXC->SW_PAD_CTL_PAD[SW_PAD_CTL_PAD_LPSPI1_PCS0_IDX] = GPIO_SW_PAD_CTL_VAL;

/* Set PCS pin direction as general-purpose output */
LPSPI1_PCS_GPIO->GDIR |= (1u << LPSPI1_PCS_GPIO_NUM);
/* Set PCS pin output as logic 1 */
LPSPI1_PCS_GPIO->DR |= (1u << LPSPI1_PCS_GPIO_NUM);

 

---

2 使能LPSPI1时钟

13.5 System Clocks

13.7.22 CCM Clock Gating Register 1 (CCM_CCGR1) 

The figure below represents the CCM Clock Gating Register 1(CCM_CCGR1). The
clock gating registers define the clock gating for power reduction of each clock (CG(i)
bits). There are 8 CGR registers. The number of registers required is determined by the
number of peripherals in the system. 

CCM->CCGR1 |= CCM_CCGR1_CG0_MASK;

---

 

3.配置lpspi时钟

/* Note: Make sure that SPI module clk freq is an even number of NOR/EEPROM clk (SPI baudrate),
*  so the duty cycle of SPI SCK can be 50% */
/* Configure SPI with a desired frequency

13.7 CCM Memory Map/Register Definition

  

13.7.6 CCM Bus Clock Multiplexer Register (CCM_CBCMR) 

/* LPSPI Clk source is controlled by CCM->CBCMR, the clk source selected for LPSPI
 *  is USB PLL (480MHz), see hapi_clock_init() in hapi_irom_clock.c 
 */
uint32_t topClkFreq = 246860000;
uint32_t podf;

uint32_t cbcmr = CCM->CBCMR & (~CCM_CBCMR_LPSPI_PODF_MASK);
podf = topClkFreq / freq;
cbcmr |= CCM_CBCMR_LPSPI_PODF(podf - 1);
CCM->CBCMR = cbcmr;