FlexSPI 引脚配置

最新推荐文章于 2023-12-09 16:53:56 发布

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最新推荐文章于 2023-12-09 16:53:56 发布

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文章标签： flexspi

本文链接：https://blog.csdn.net/l3142600073/article/details/107717981

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RT1020 FlexSPI 引脚配置

/** IOMUXC - Register Layout Typedef */
typedef struct {
       uint8_t RESERVED_0[20];
  __IO uint32_t SW_MUX_CTL_PAD[93]; /**< SW_MUX_CTL_PAD_GPIO_EMC_00 SW MUX Control Register..SW_MUX_CTL_PAD_GPIO_SD_B1_11 SW MUX Control Register, array offset: 0x14, array step: 0x4 */
  __IO uint32_t SW_PAD_CTL_PAD[93]; /**< SW_PAD_CTL_PAD_GPIO_EMC_00 SW PAD Control Register..SW_PAD_CTL_PAD_GPIO_SD_B1_11 SW PAD Control Register, array offset: 0x188, array step: 0x4 */
  __IO uint32_t SELECT_INPUT[114];  /**< ANATOP_USB_OTG_ID_SELECT_INPUT DAISY Register..XBAR1_IN19_SELECT_INPUT DAISY Register, array offset: 0x2FC, array step: 0x4 */
} IOMUXC_Type

以 FLEXSPI _A_DATA0 为例，配置 GPIO_SD_B1_08 引脚，首先是引脚复用，然后配置引脚属性，最后设置 DAISY

1 引脚复用

2 配置IO 寄存器属性

3 设置 DAISY

#define FLEXSPI_SW_PAD_CTL_VAL                                                                      \
    (IOMUXC_SW_PAD_CTL_PAD_SRE(1) | IOMUXC_SW_PAD_CTL_PAD_DSE(6) | IOMUXC_SW_PAD_CTL_PAD_SPEED(3) | \
     IOMUXC_SW_PAD_CTL_PAD_PKE(1) | IOMUXC_SW_PAD_CTL_PAD_PUE(0) | IOMUXC_SW_PAD_CTL_PAD_PUS(0))
// FLEXSPIA_DATA0
IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_02] = FLEXSPIA_SEC_MUX_VAL; //引脚复用
IOMUXC->SW_PAD_CTL_PAD[kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_02] = FLEXSPI_SW_PAD_CTL_VAL //配置引脚属性
IOMUXC->SELECT_INPUT[kIOMUXC_FLEXSPI_A_DATA0_SELECT_INPUT] = 0x01;