linux clock

linux clock  

/**

 * struct clk_ops - standard clock operations

 * @set_rate: set the clock rate, see clk_set_rate().

 * @get_rate: get the clock rate, see clk_get_rate().

 * @round_rate: round a given clock rate, see clk_round_rate().

 * @set_parent: set the clock's parent, see clk_set_parent().

 *

 * Group the common clock implementations together so that we

 * don't have to keep setting the same fiels again. We leave

 * enable in struct clk.

 *

 * Adding an extra layer of indirection into the process should

 * not be a problem as it is unlikely these operations are going

 * to need to be called quickly.

 */

struct clk_ops {

int    (*set_rate)(struct clk *c, unsigned long rate);

unsigned long    (*get_rate)(struct clk *c);

unsigned long    (*round_rate)(struct clk *c, unsigned long rate);

int    (*set_parent)(struct clk *c, struct clk *parent);

};

struct clk {

struct list_head      list;

struct module        *owner;

struct clk           *parent;

const char           * name;

int       id;

int      usage;

unsigned long         rate;

unsigned long         ctrlbit;

struct clk_ops *ops;

int    (*enable)(struct clk *, int enable);

};

/**

 * struct clksrc_sources - list of sources for a given clock

 * @sources: array of pointers to clocks

 * @nr_sources: The size of @sources

 */

struct clksrc_sources {

unsigned int nr_sources;

struct clk **sources;

};

/**

 * struct clksrc_reg - register definition for clock control bits

 * @reg: pointer to the register in virtual memory.

 * @shift: the shift in bits to where the bitfield is.

 * @size: the size in bits of the bitfield.

 *

 * This specifies the size and position of the bits we are interested

 * in within the register specified by @reg.

 */

struct clksrc_reg {

void __iomem *reg;

unsigned short shift;

unsigned short size;

};

/**

 * struct clksrc_clk - class of clock for newer style samsung devices.

 * @clk: the standard clock representation

 * @sources: the sources for this clock

 * @reg_src: the register definition for selecting the clock's source

 * @reg_div: the register definition for the clock's output divisor

 *

 * This clock implements the features required by the newer SoCs where

 * the standard clock block provides an input mux and a post-mux divisor

 * to provide the periperhal's clock.

 *

 * The array of @sources provides the mapping of mux position to the

 * clock, and @reg_src shows the code where to modify to change the mux

 * position. The @reg_div defines how to change the divider settings on

 * the output.

 */

struct clksrc_clk {

struct clk clk;

struct clksrc_sources *sources;

struct clksrc_reg reg_src;

struct clksrc_reg reg_div;

};

/* MOUT APLL */

static struct clksrc_clk clk_mout_apll = {

.clk = {

.name = "mout_apll",

.id = -1,

},

.sources = & clk_src_apll,

.reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },

};

/* MOUT MPLL */

static struct clksrc_clk clk_mout_mpll = {

.clk = {

.name = "mout_mpll",

.id = -1,

},

.sources = &clk_src_mpll,

.reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },

};

/* MOUT EPLL */

static struct clksrc_clk clk_mout_epll = {

.clk = {

.name = "mout_epll",

.id = -1,

},

.sources = &clk_src_epll,

.reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },

};

/* Possible clock sources for APLL Mux */

static struct clk * clk_src_apll_list[] = {

[0] = & clk_fin_apll,

[1] = &clk_fout_apll,

};

struct clksrc_sources clk_src_apll = {

.sources = clk_src_apll_list,

.nr_sources = ARRAY_SIZE(clk_src_apll_list),

};

/* Possible clock sources for MPLL Mux */

static struct clk *clk_src_mpll_list[] = {

[0] = &clk_fin_mpll,

[1] = &clk_fout_mpll,

};

struct clksrc_sources clk_src_mpll = {

.sources = clk_src_mpll_list,

.nr_sources = ARRAY_SIZE(clk_src_mpll_list),

};

/* Possible clock sources for EPLL Mux */

static struct clk *clk_src_epll_list[] = {

[0] = &clk_fin_epll,

[1] = &clk_fout_epll,

};

struct clksrc_sources clk_src_epll = {

.sources = clk_src_epll_list,

.nr_sources = ARRAY_SIZE(clk_src_epll_list),

};

#define clk_fin_apll clk_ext_xtal_mux

#define clk_fin_mpll clk_ext_xtal_mux

#define clk_fin_epll clk_ext_xtal_mux

#define clk_fin_vpll clk_ext_xtal_mux

/* fin_apll, fin_mpll and fin_epll are all the same clock, which we call

 * clk_ext_xtal_mux.

*/

struct clk clk_ext_xtal_mux = {

.name = "ext_xtal",

.id = -1,

};

获取时钟，和频率

xtal_clk = clk_get(NULL, "ext_xtal");

xtal = clk_get_rate(xtal_clk);