BTL_RX_7S

`timescale 1ns / 1ps
module BTL_RX_7S(
input				clk,
input				srst,
input				rxd,
(* MARK_DEBUG="true" *)output				m_axis_tvalid,
(* MARK_DEBUG="true" *)output	[ 7: 0]		m_axis_tdata
);
parameter	FP = 400;
parameter	BFP = 200;

parameter	IDLE = 1'b0;
parameter	S1   = 1'b1;
(* MARK_DEBUG="true" *)reg					state_c = 1'b0;
reg					state_n;
wire				idle2s1_start;
wire				s12idle_start;

reg					rxd_r1 = 1'b0;
reg					rxd_r2 = 1'b0;
(* MARK_DEBUG="true" *)reg					rxd_r3 = 1'b0;
wire				rxd_n;

(* MARK_DEBUG="true" *)reg		[15: 0]		cnt = 'd0;
wire				add_cnt;
wire				end_cnt;
(* MARK_DEBUG="true" *)reg		[ 3: 0]		cnt1 = 'd0;
wire				add_cnt1;
wire				end_cnt1;

reg		[ 7: 0]		yiwei_r = 8'h00;

always	@(posedge clk)begin
	if(srst)begin
		rxd_r1 <= 1'b0;
		rxd_r2 <= 1'b0;
		rxd_r3 <= 1'b0;
	end
	else begin
		rxd_r1 <= rxd;
		rxd_r2 <= rxd_r1;
		rxd_r3 <= rxd_r2;
	end
end
assign	rxd_n = rxd_r3 && (!rxd_r2);

always	@(posedge clk)begin
	if(srst)begin
		state_c <= IDLE;
	end
	else begin
		state_c <= state_n;
	end
end

always	@(*)begin
	case(state_c)
		IDLE:begin
			if(idle2s1_start)begin
				state_n = S1;
			end
			else begin
				state_n = IDLE;
			end
		end
		S1:begin
			if(s12idle_start)begin
				state_n = IDLE;
			end
			else begin
				state_n = S1;
			end
		end
		default:begin
			state_n = IDLE;
		end
	endcase
end
assign	idle2s1_start = state_c == IDLE && rxd_n;
assign	s12idle_start = state_c == S1   && end_cnt1;


always	@(posedge clk)begin
	if(srst)begin
		cnt <= 'd0;
	end
	else if(add_cnt)begin
		if(end_cnt)begin
			cnt <= 0;
		end
		else begin
			cnt <= cnt + 1'b1;
		end
	end
end
assign	add_cnt = state_c == S1;
assign	end_cnt = add_cnt && cnt == FP - 1;


always	@(posedge clk)begin
	if(srst)begin
		cnt1 <= 'd0;
	end
	else if(add_cnt1)begin
		if(end_cnt1)begin
			cnt1 <= 0;
		end
		else begin
			cnt1 <= cnt1 + 1'b1;
		end
	end
end
assign	add_cnt1 = end_cnt;
assign	end_cnt1 = add_cnt1 && cnt1 == 9 - 1;

always	@(posedge clk)begin
	if(srst)begin
		yiwei_r <= 8'h00;
	end
	else if(cnt == BFP - 1)begin
		yiwei_r <= {rxd_r3,yiwei_r[7:1]};
	end
end
assign	m_axis_tdata  = yiwei_r;
assign	m_axis_tvalid = end_cnt1;

endmodule