BTL_TX_7S

`timescale 1ns / 1ps
module BTL_TX_7S(
input				clk,
input				srst,
output				txd,
(* MARK_DEBUG="true" *)output				s_axis_tready,
(* MARK_DEBUG="true" *)input				s_axis_tvalid,
(* MARK_DEBUG="true" *)input	[ 7: 0]		s_axis_tdata
);
parameter	FP = 400;
parameter	BFP = 200;

parameter	IDLE = 2'd0;
parameter	S1   = 2'd1;
parameter	S2   = 2'd2;
(* MARK_DEBUG="true" *)reg		[ 1: 0]		state_c = 2'd0;
reg		[ 1: 0]		state_n;
wire				idle2s2_start;
wire				s12s2_start;
wire				s22s1_start;

(* MARK_DEBUG="true" *)reg		[15: 0]		cnt = 'd0;
wire				add_cnt;
wire				end_cnt;
(* MARK_DEBUG="true" *)reg		[ 3: 0]		cnt1 = 'd0;
wire				add_cnt1;
wire				end_cnt1;

(* MARK_DEBUG="true" *)reg		[ 9: 0]		yiwei_r = 10'h3ff;

always	@(posedge clk)begin
	if(srst)begin
		state_c <= IDLE;
	end
	else begin
		state_c <= state_n;
	end
end

always	@(*)begin
	case(state_c)
		IDLE:begin
			if(idle2s2_start)begin
				state_n = S2;
			end
			else begin
				state_n = IDLE;
			end
		end
		S1:begin
			if(s12s2_start)begin
				state_n = S2;
			end
			else begin
				state_n = S1;
			end
		end
		S2:begin
			if(s22s1_start)begin
				state_n = S1;
			end
			else begin
				state_n = S2;
			end
		end
		default:begin
			state_n = IDLE;
		end
	endcase
end
assign	idle2s2_start = state_c == IDLE && 1'b1;
assign	s12s2_start   = state_c == S1   && s_axis_tvalid;
assign	s22s1_start   = state_c == S2   && end_cnt1;
assign	s_axis_tready = state_c == S1;

always	@(posedge clk)begin
	if(srst)begin
		cnt <= 'd0;
	end
	else if(add_cnt)begin
		if(end_cnt)begin
			cnt <= 0;
		end
		else begin
			cnt <= cnt + 1'b1;
		end
	end
end
assign	add_cnt = state_c == S2;
assign	end_cnt = add_cnt && cnt == FP - 1;


always	@(posedge clk)begin
	if(srst)begin
		cnt1 <= 'd0;
	end
	else if(add_cnt1)begin
		if(end_cnt1)begin
			cnt1 <= 0;
		end
		else begin
			cnt1 <= cnt1 + 1'b1;
		end
	end
end
assign	add_cnt1 = end_cnt;
assign	end_cnt1 = add_cnt1 && cnt1 == 10 - 1;

always	@(posedge clk)begin
	if(srst)begin
		yiwei_r <= 10'h3ff;
	end
	else if(s12s2_start)begin
		yiwei_r <= {1'b1,s_axis_tdata,1'b0};
	end
	else if(end_cnt)begin
		yiwei_r <= {1'b1,yiwei_r[9:1]};
	end
end
assign	txd = yiwei_r[0];

endmodule