System Verilog 数据类型练习

SV数据类型
默认有符号数
integer i; //4态， 32bits，signed
byte b8;//2态， 8bits，signed integer
int i;//2态， 32bits，signed integer
shortint s;//2态， 16bits，signed integer
longint l;//2态， 64bits，signed integer

默认无符号数
bit b;//2态
reg r;//4态
logic w;//4态

数组Array
非合并数组：bit [31:0] d [3:0] ;[3:0]为高维，4个字节空间

bit [3:0] [7:0] bytes; [3:0]为高维，4个字节组装成32bit

数组练习：test_array.sv文件

class Array;
  int array[9:0] ;
  
  function new();
     for( int i = 0 ; i < 10 ; i++ )
         array[i] = i ;
  endfunction:new
  
   function void print();
    foreach(array[i]) begin
      $display(" array[%d] = %d ",i,array[i]);
    end
    for ( int i = 0 ; i < 10 ; i++ )begin
      $write(" ** ");
    end
    $display();
  endfunction:print
  
  function void funcs();
      int pos[$] ;
    $display("the sum is %d ",array.sum());
    $display("the and is %d ",array.and());
    $display("the  or is %d ",array.or() );
    $display("the xor is %d ",array.xor());
    $display("the product is %d ",array.product());
    
    //$display(" max value is %d ",array.max()[0]);
    //$display(" min value is %d ",array.min()[0]);
    $display(" max value is %d ",array.max());
    $display(" min value is %d ",array.min());
    //array = array.unique();
    //print();       
    pos = array.find with ( item == 7 ) ; 
    //  find  find_first   find_last  find_first_index   find_last_index
    $display(" pos : %d ? value: %d ",pos[0],array[pos[0]]);
    
    //   sort ,  rsort  , reverse , shuffle , 
    array.shuffle();
    $display("shuffled:");
    print();
    array.sort();
    $display("Sorted:");
    print();
    array.rsort();
    $display("Resorted:");
    print();
    array.reverse();
    $display("Reversed:");
    print();  
  endfunction:funcs
endclass:Array

module top;
  Array array;
  int arr[] ;     
  
  initial begin
    //  initial process
    array=new();
    array.print();
    array.funcs();
    arr = new[20];  
    foreach(arr[i]) $display(" arr[%2d] = %d ",i,arr[i]); 
    $display("***************");
    arr.delete();
  end
endmodule

编译vcs -full64 -sverilog -debug-all test_array.sv
仿真./simv
结果
array[ 9] = 9
array[ 8] = 8
array[ 7] = 7
array[ 6] = 6
array[ 5] = 5
array[ 4] = 4
array[ 3] = 3
array[ 2] = 2
array[ 1] = 1
array[ 0] = 0

---

the sum is 45
the and is 0
the or is 15
the xor is 1
the product is 0
max value is -1205066320
min value is -1205065584
pos : 7 ? value: 7
shuffled:
array[ 9] = 1
array[ 8] = 3
array[ 7] = 2
array[ 6] = 0
array[ 5] = 4
array[ 4] = 9
array[ 3] = 8
array[ 2] = 5
array[ 1] = 7
array[ 0] = 6

---

Sorted:
array[ 9] = 0
array[ 8] = 1
array[ 7] = 2
array[ 6] = 3
array[ 5] = 4
array[ 4] = 5
array[ 3] = 6
array[ 2] = 7
array[ 1] = 8
array[ 0] = 9

---

Resorted:
array[ 9] = 9
array[ 8] = 8
array[ 7] = 7
array[ 6] = 6
array[ 5] = 5
array[ 4] = 4
array[ 3] = 3
array[ 2] = 2
array[ 1] = 1
array[ 0] = 0

---

Reversed:
array[ 9] = 0
array[ 8] = 1
array[ 7] = 2
array[ 6] = 3
array[ 5] = 4
array[ 4] = 5
array[ 3] = 6
array[ 2] = 7
array[ 1] = 8
array[ 0] = 9

---

arr[ 0] = 0
arr[ 1] = 0
arr[ 2] = 0
arr[ 3] = 0
arr[ 4] = 0
arr[ 5] = 0
arr[ 6] = 0
arr[ 7] = 0
arr[ 8] = 0
arr[ 9] = 0
arr[10] = 0
arr[11] = 0
arr[12] = 0
arr[13] = 0
arr[14] = 0
arr[15] = 0
arr[16] = 0
arr[17] = 0
arr[18] = 0
arr[19] = 0

---

枚举类型test_enum

module test_enum;
typedef enum{IDLE, TEST, START}state_t;
enum bit [2:0]{S0='b001,S1='b010, S2='b100}st;
state_t c_st, n_st=IDLE;
initial begin
	$display("###############################");
	$display("st=%3b, n_st=%s",st.first,n_st.name());
	$display("st=%3b, n_st=%s",st.last,n_st.name());
	$display("st=%3b, n_st=%s",c_st.next(2),n_st.first);

end
endmodule

编译，仿真结果
###############################
st=001, n_st=IDLE
st=100, n_st=IDLE
st=010, n_st=IDLE

队列test_queue

module test_queue;
int j =2;
int q[$] ={0,1,3,6};
int b[$] ={4,5};


function void disp();
	$display("------------------------");
	foreach(q[i]) begin
		$display("INDEX : %d Value: %d",i,q[i]);
	end
endfunction


typedef struct packed {
        logic [15:0] sa;
        logic [15:0] da;
        logic [31:0] data;
} packet_t;
union packed { 
        packet_t data_packet;
        logic [63:0] bit_slice;
        logic [7:0][7:0] byte_slice;
} u_dreg;


initial begin
disp();
q.insert(2,j);
disp();
//q.insert(4,b);
//disp();
q.delete(1);
disp();
q.push_front(7);
disp();
j=q.pop_back();
disp();
$display(j);
$display($size(q));
q.delete();
$display(q.size());

//q.pop_front(u_dreg);
//disp();

end
endmodule

编译，仿真结果

INDEX : 0 Value: 0
INDEX : 1 Value: 1
INDEX : 2 Value: 3
INDEX : 3 Value: 6

INDEX : 0 Value: 0
INDEX : 1 Value: 1
INDEX : 2 Value: 2
INDEX : 3 Value: 3
INDEX : 4 Value: 6

INDEX : 0 Value: 0
INDEX : 1 Value: 2
INDEX : 2 Value: 3
INDEX : 3 Value: 6

INDEX : 0 Value: 7
INDEX : 1 Value: 0
INDEX : 2 Value: 2
INDEX : 3 Value: 3
INDEX : 4 Value: 6

INDEX : 0 Value: 7
INDEX : 1 Value: 0
INDEX : 2 Value: 2
INDEX : 3 Value: 3
6
4
0