xilinx_ug903阅读记录

1

• 将时序约束与物理约束分开,并保存为两组分开的文件
• 可以针对某个模块,使用单独的约束文件进行约束
• IP的约束不显示在约束set中，它们存在于IP的源文件路径下
• 默认情况下,所有的XDC和Tcl对综合/实现都起作用。不过，可以通过设置USED_IN_SYNTHESIS和USED_IN_IMPLEMENTATION属性来改变它们的行为
• XDC约束是顺序执行的,且是基于优先级的
• 可以使用report_compile_order -constraints来获得XDC文件的读入顺序

2

推荐的约束顺序为
Timing Assertions Section

• Primary clocks
• Virtual clocks
• Generated clocks
• Clock Groups
• Bus Skew constraints
• Input and output delay constraints

Timing Exceptions Section

• False Paths
• Max Delay / Min Delay
• Multicycle Paths
• Case Analysis
• Disable Timing

Physical Constraints Section

• located anywhere in the file, preferably before or after the timing constraints or stored in a separate constraint file

3

Vivado的约束管理器会将修改的约束保存到它的原XDC文件中。任何的新的约束会被保存在标记为target的XDC文件的末尾。

RECOMMENDED:Xilinx recommends that you separate timing constraints and physical constraints by saving them into two distinct files. You can also keep the constraints specific to a certain module in a separate file.

IMPORTANT: If your project contains an IP that uses its own constraints, the corresponding constraint file does not appear in the constraints set. Instead, it is listed along with the IP source files.