core-v-verif系列之cva6 verilator Model编译-CSDN博客

本文链接：https://blog.csdn.net/lincolnjunior_lj/article/details/146342885

编译命令

单个case 执行日志

Wed, 19 Mar 2025 11:18:28 DEBUG    mkdir -p /cva6/verif/sim/out_2025-03-19-5966/directed_tests
Wed, 19 Mar 2025 11:18:28 DEBUG    
Wed, 19 Mar 2025 11:18:28 INFO     Compiling test: /cva6/verif/tests/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/addi-01.S
Wed, 19 Mar 2025 11:18:28 DEBUG    /RISCV_TOOLS/bin/riscv-none-elf-gcc /cva6/verif/tests/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/addi-01.S           -I/cva6/verif/sim/dv/user_extension             -T../tests/riscv-arch-test/riscv-target/spike/link.ld -DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/cva6/verif/tests/riscv-arch-test/riscv-test-suite/env/ -I/cva6/verif/tests/riscv-arch-test/riscv-target/spike/ -o /cva6/verif/sim/out_2025-03-19-5966/directed_tests/addi-01.o  -march=rv64gc_zba_zbb_zbs_zbc -mabi=lp64d
Wed, 19 Mar 2025 11:18:29 DEBUG    
Wed, 19 Mar 2025 11:18:29 DEBUG    mkdir -p /cva6/verif/sim/out_2025-03-19-5966/spike_sim
Wed, 19 Mar 2025 11:18:29 DEBUG    
Wed, 19 Mar 2025 11:18:29 INFO     Processing ISS setup file: cva6.yaml
Wed, 19 Mar 2025 11:18:29 INFO     Found matching ISS: spike
Wed, 19 Mar 2025 11:18:29 INFO     Target: cv64a6_imafdc_sv39
Wed, 19 Mar 2025 11:18:29 INFO     ISA rv64gc_zba_zbb_zbs_zbc
Wed, 19 Mar 2025 11:18:29 INFO     [spike] Running ISS simulation: make spike steps=2000000 target=cv64a6_imafdc_sv39 variant=rv64gc_zba_zbb_zbs_zbc priv=msu elf=/cva6/verif/sim/out_2025-03-19-5966/directed_tests/addi-01.o tool_path=/cva6/tools/spike/bin log=/cva6/verif/sim/out_2025-03-19-5966/spike_sim/rv64i_m-addi-01.cv64a6_imafdc_sv39.log spike_params='' &> /cva6/verif/sim/out_2025-03-19-5966/spike_sim/rv64i_m-addi-01.cv64a6_imafdc_sv39.log.iss
Wed, 19 Mar 2025 11:18:29 DEBUG    make spike steps=2000000 target=cv64a6_imafdc_sv39 variant=rv64gc_zba_zbb_zbs_zbc priv=msu elf=/cva6/verif/sim/out_2025-03-19-5966/directed_tests/addi-01.o tool_path=/cva6/tools/spike/bin log=/cva6/verif/sim/out_2025-03-19-5966/spike_sim/rv64i_m-addi-01.cv64a6_imafdc_sv39.log spike_params='' &> /cva6/verif/sim/out_2025-03-19-5966/spike_sim/rv64i_m-addi-01.cv64a6_imafdc_sv39.log.iss
Wed, 19 Mar 2025 11:18:29 DEBUG    
Wed, 19 Mar 2025 11:18:29 INFO     [spike] Running ISS simulation: /cva6/verif/sim/out_2025-03-19-5966/directed_tests/addi-01.o ...done
Wed, 19 Mar 2025 11:18:29 DEBUG    mkdir -p /cva6/verif/sim/out_2025-03-19-5966/veri-testharness_sim
Wed, 19 Mar 2025 11:18:29 DEBUG    
Wed, 19 Mar 2025 11:18:29 INFO     Processing ISS setup file: cva6.yaml
Wed, 19 Mar 2025 11:18:29 INFO     Found matching ISS: veri-testharness
Wed, 19 Mar 2025 11:18:29 INFO     Target: cv64a6_imafdc_sv39
Wed, 19 Mar 2025 11:18:29 INFO     ISA rv64gc_zba_zbb_zbs_zbc
Wed, 19 Mar 2025 11:18:29 INFO     [veri-testharness] Running ISS simulation: make veri-testharness target=cv64a6_imafdc_sv39 variant=rv64gc_zba_zbb_zbs_zbc elf=/cva6/verif/sim/out_2025-03-19-5966/directed_tests/addi-01.o path_var=/cva6/ tool_path=/cva6/tools/spike/bin isscomp_opts="" issrun_opts="+tb_performance_mode+debug_disable=1+UVM_VERBOSITY=UVM_NONE +ntb_random_seed=1877498032" isspostrun_opts="0x0000000080000000" log=/cva6/verif/sim/out_2025-03-19-5966/veri-testharness_sim/rv64i_m-addi-01.cv64a6_imafdc_sv39.log &> /cva6/verif/sim/out_2025-03-19-5966/veri-testharness_sim/rv64i_m-addi-01.cv64a6_imafdc_sv39.log.iss
Wed, 19 Mar 2025 11:18:29 DEBUG    make veri-testharness target=cv64a6_imafdc_sv39 variant=rv64gc_zba_zbb_zbs_zbc elf=/cva6/verif/sim/out_2025-03-19-5966/directed_tests/addi-01.o path_var=/cva6/ tool_path=/cva6/tools/spike/bin isscomp_opts="" issrun_opts="+tb_performance_mode+debug_disable=1+UVM_VERBOSITY=UVM_NONE +ntb_random_seed=1877498032" isspostrun_opts="0x0000000080000000" log=/cva6/verif/sim/out_2025-03-19-5966/veri-testharness_sim/rv64i_m-addi-01.cv64a6_imafdc_sv39.log &> /cva6/verif/sim/out_2025-03-19-5966/veri-testharness_sim/rv64i_m-addi-01.cv64a6_imafdc_sv39.log.iss
Wed, 19 Mar 2025 11:18:41 DEBUG    
Wed, 19 Mar 2025 11:18:41 INFO     [veri-testharness] Running ISS simulation: /cva6/verif/sim/out_2025-03-19-5966/directed_tests/addi-01.o ...done
Wed, 19 Mar 2025 11:18:41 INFO     Processing spike log : /cva6/verif/sim/out_2025-03-19-5966/spike_sim/rv64i_m-addi-01.cv64a6_imafdc_sv39.log
Wed, 19 Mar 2025 11:18:41 INFO     Processed instruction count : 4793
Wed, 19 Mar 2025 11:18:41 INFO     CSV saved to : /cva6/verif/sim/out_2025-03-19-5966/spike_sim/rv64i_m-addi-01.cv64a6_imafdc_sv39.csv
Wed, 19 Mar 2025 11:18:41 INFO     Processing verilator log : /cva6/verif/sim/out_2025-03-19-5966/veri-testharness_sim/rv64i_m-addi-01.cv64a6_imafdc_sv39.log
Wed, 19 Mar 2025 11:18:41 INFO     Processed instruction count : 4792
Wed, 19 Mar 2025 11:18:41 INFO     CSV saved to : /cva6/verif/sim/out_2025-03-19-5966/veri-testharness_sim/rv64i_m-addi-01.cv64a6_imafdc_sv39.csv
Wed, 19 Mar 2025 11:18:41 INFO     [PASSED]: 3882 matched

其中，make veri-testharness 为编译 model 命令：

 make veri-testharness target=cv64a6_imafdc_sv39 variant=rv64gc_zba_zbb_zbs_zbc elf=/cva6/verif/sim/out_2025-03-19-5966/directed_tests/addi-01.o path_var=/cva6/ tool_path=/cva6/tools/spike/bin isscomp_opts="" issrun_opts="+tb_performance_mode+debug_disable=1+UVM_VERBOSITY=UVM_NONE +ntb_random_seed=1877498032" isspostrun_opts="0x0000000080000000" log=/cva6/verif/sim/out_2025-03-19-5966/veri-testharness_sim/rv64i_m-addi-01.cv64a6_imafdc_sv39.log &> /cva6/verif/sim/out_2025-03-19-5966/veri-testharness_sim/rv64i_m-addi-01.cv64a6_imafdc_sv39.log.iss

Makefile 路径cva6/verif/sim/Makefile

veri-testharness:
	@echo "veri-testharness target--->"
	make -C $(path_var) verilate verilator="verilator --no-timing" target=$(target) defines=$(subst +define+,,$(isscomp_opts))
	$(path_var)/work-ver/Variane_testharness $(if $(TRACE_COMPACT), -f verilator.fst) $(if $(TRACE_FAST), -v verilator.vcd) $(elf) $(issrun_opts) \
	  $(COMMON_PLUS_ARGS)
	# If present, move default waveform files to log directory.
	# Keep track of target in waveform file name.
	[ ! -f verilator.fst ] || mv verilator.fst `dirname $(log)`/`basename $(log) .log`.fst
	[ ! -f verilator.vcd ] || mv verilator.vcd `dirname $(log)`/`basename $(log) .log`.vcd
	# Generate disassembled log.
	$(tool_path)/spike-dasm --isa=$(variant) < ./trace_rvfi_hart_00.dasm > $(log)
	grep $(isspostrun_opts) ./trace_rvfi_hart_00.dasm

其中， make -C $(path_var) verilate 为编译

Makefile 路径/cva6/Makefile

# User Verilator, at some point in the future this will be auto-generated
verilate:
	@echo "[Verilator] Building Model$(if $(PROFILE), for Profiling,)"
	$(verilate_command)
	cd $(ver-library) && $(MAKE) -j${NUM_JOBS} -f Variane_testharness.mk

编译 model command： verilate_command


# verilator-specific
verilate_command := $(verilator) --no-timing verilator_config.vlt                                                \
                    -f core/Flist.cva6                                                                           \
                    core/cva6_rvfi.sv                                                                            \
                    $(filter-out %.vhd, $(ariane_pkg))                                                           \
                    $(filter-out core/fpu_wrap.sv, $(filter-out %.vhd, $(filter-out %_config_pkg.sv, $(src))))   \
                    +define+$(defines)$(if $(TRACE_FAST),+VM_TRACE)$(if $(TRACE_COMPACT),+VM_TRACE+VM_TRACE_FST) \
                    corev_apu/tb/common/mock_uart.sv                                                             \
                    +incdir+corev_apu/axi_node                                                                   \
                    $(if $(verilator_threads), --threads $(verilator_threads))                                   \
                    --unroll-count 256                                                                           \
                    -Wall                                                                                        \
                    -Werror-PINMISSING                                                                           \
                    -Werror-IMPLICIT                                                                             \
                    -Wno-fatal                                                                                   \
                    -Wno-PINCONNECTEMPTY                                                                         \
                    -Wno-ASSIGNDLY                                                                               \
                    -Wno-DECLFILENAME                                                                            \
                    -Wno-UNUSED                                                                                  \
                    -Wno-UNOPTFLAT                                                                               \
                    -Wno-BLKANDNBLK                                                                              \
                    -Wno-style                                                                                   \
                    $(if ($(PRELOAD)!=""), -DPRELOAD=1,)                                                         \
                    $(if $(PROFILE),--stats --stats-vars --profile-cfuncs,)                                      \
                    $(if $(DEBUG), --trace-structs,)                                                             \
                    $(if $(TRACE_COMPACT), --trace-fst $(VL_INC_DIR)/verilated_fst_c.cpp)                        \
                    $(if $(TRACE_FAST), --trace $(VL_INC_DIR)/verilated_vcd_c.cpp)                               \
                    -LDFLAGS "-L$(RISCV)/lib -L$(SPIKE_INSTALL_DIR)/lib -Wl,-rpath,$(RISCV)/lib -Wl,-rpath,$(SPIKE_INSTALL_DIR)/lib -lfesvr -lriscv -ldisasm -lyaml-cpp $(if $(PROFILE), -g -pg,) -lpthread $(if $(TRACE_COMPACT), -lz,)" \
                    -CFLAGS "$(CFLAGS)$(if $(PROFILE), -g -pg,) -DVL_DEBUG -I$(SPIKE_INSTALL_DIR)"               \
                    $(if $(SPIKE_TANDEM), +define+SPIKE_TANDEM, )                                                \
                    --cc --vpi                                                                                   \
                    $(list_incdir) --top-module ariane_testharness                                               \
                    --threads-dpi none                                                                           \
                    --Mdir $(ver-library) -O3                                                                    \
                    --exe corev_apu/tb/ariane_tb.cpp corev_apu/tb/dpi/SimDTM.cc corev_apu/tb/dpi/SimJTAG.cc      \
                    corev_apu/tb/dpi/remote_bitbang.cc corev_apu/tb/dpi/msim_helper.cc

编译执行输出日志


make -C 
/home/cva6/ verilate verilator="verilator --no-timing" target=cv64a6_imafdc_sv39 defines=
make[1]: Entering directory '/home/cva6'
Makefile:153: XCELIUM_HOME not set which is necessary for compiling DPIs when using XCELIUM
[Verilator] Building Model
verilator --no-timing --no-timing verilator_config.vlt 
-f core/Flist.cva6 core/cva6_rvfi.sv 
/home/cva6/corev_apu/tb/ariane_axi_pkg.sv 
/home/cva6/corev_apu/tb/axi_intf.sv 
/home/cva6/corev_apu/register_interface/src/reg_intf.sv 
/home/cva6/corev_apu/tb/ariane_soc_pkg.sv 
/home/cva6/corev_apu/riscv-dbg/src/dm_pkg.sv 
/home/cva6/corev_apu/tb/ariane_axi_soc_pkg.sv 
/home/cva6/core/cva6_rvfi.sv 
/home/cva6/corev_apu/src/ariane.sv 
/home/cva6/corev_apu/bootrom/bootrom.sv 
/home/cva6/corev_apu/clint/axi_lite_interface.sv 
/home/cva6/corev_apu/clint/clint.sv 
/home/cva6/corev_apu/fpga/src/axi2apb/src/axi2apb_64_32.sv 
/home/cva6/corev_apu/fpga/src/axi2apb/src/axi2apb.sv 
/home/cva6/corev_apu/fpga/src/axi2apb/src/axi2apb_wrap.sv 
/home/cva6/corev_apu/fpga/src/apb_timer/apb_timer.sv 
/home/cva6/corev_apu/fpga/src/apb_timer/timer.sv 
/home/cva6/corev_apu/fpga/src/axi_slice/src/axi_ar_buffer.sv 
/home/cva6/corev_apu/fpga/src/axi_slice/src/axi_aw_buffer.sv 
/home/cva6/corev_apu/fpga/src/axi_slice/src/axi_b_buffer.sv 
/home/cva6/corev_apu/fpga/src/axi_slice/src/axi_r_buffer.sv 
/home/cva6/corev_apu/fpga/src/axi_slice/src/axi_single_slice.sv 
/home/cva6/corev_apu/fpga/src/axi_slice/src/axi_slice.sv 
/home/cva6/corev_apu/fpga/src/axi_slice/src/axi_slice_wrap.sv 
/home/cva6/corev_apu/fpga/src/axi_slice/src/axi_w_buffer.sv 
/home/cva6/corev_apu/src/axi_riscv_atomics/src/axi_res_tbl.sv 
/home/cva6/corev_apu/src/axi_riscv_atomics/src/axi_riscv_amos_alu.sv 
/home/cva6/corev_apu/src/axi_riscv_atomics/src/axi_riscv_amos.sv 
/home/cva6/corev_apu/src/axi_riscv_atomics/src/axi_riscv_atomics.sv 
/home/cva6/corev_apu/src/axi_riscv_atomics/src/axi_riscv_atomics_wrap.sv 
/home/cva6/corev_apu/src/axi_riscv_atomics/src/axi_riscv_lrsc.sv 
/home/cva6/corev_apu/src/axi_riscv_atomics/src/axi_riscv_lrsc_wrap.sv 
/home/cva6/corev_apu/axi_mem_if/src/axi2mem.sv 
/home/cva6/corev_apu/riscv-dbg/src/dm_csrs.sv 
/home/cva6/corev_apu/riscv-dbg/src/dmi_cdc.sv 
/home/cva6/corev_apu/riscv-dbg/src/dmi_jtag.sv 
/home/cva6/corev_apu/riscv-dbg/src/dmi_jtag_tap.sv 
/home/cva6/corev_apu/riscv-dbg/src/dm_mem.sv 
/home/cva6/corev_apu/riscv-dbg/src/dm_sba.sv 
/home/cva6/corev_apu/riscv-dbg/src/dm_top.sv 
/home/cva6/corev_apu/rv_plic/rtl/rv_plic_target.sv 
/home/cva6/corev_apu/rv_plic/rtl/rv_plic_gateway.sv 
/home/cva6/corev_apu/rv_plic/rtl/plic_regmap.sv 
/home/cva6/corev_apu/rv_plic/rtl/plic_top.sv 
/home/cva6/corev_apu/riscv-dbg/debug_rom/debug_rom.sv 
/home/cva6/corev_apu/register_interface/src/apb_to_reg.sv 
/home/cva6/vendor/pulp-platform/axi/src/axi_multicut.sv 
/home/cva6/vendor/pulp-platform/common_cells/src/rstgen_bypass.sv 
/home/cva6/vendor/pulp-platform/common_cells/src/rstgen.sv 
/home/cva6/vendor/pulp-platform/common_cells/src/addr_decode.sv 
/home/cva6/vendor/pulp-platform/common_cells/src/stream_register.sv 
/home/cva6/vendor/pulp-platform/axi/src/axi_cut.sv 
/home/cva6/vendor/pulp-platform/axi/src/axi_join.sv 
/home/cva6/vendor/pulp-platform/axi/src/axi_delayer.sv 
/home/cva6/vendor/pulp-platform/axi/src/axi_to_axi_lite.sv 
/home/cva6/vendor/pulp-platform/axi/src/axi_id_prepend.sv 
/home/cva6/vendor/pulp-platform/axi/src/axi_atop_filter.sv 
/home/cva6/vendor/pulp-platform/axi/src/axi_err_slv.sv 
/home/cva6/vendor/pulp-platform/axi/src/axi_mux.sv 
/home/cva6/vendor/pulp-platform/axi/src/axi_demux.sv 
/home/cva6/vendor/pulp-platform/axi/src/axi_xbar.sv 
/home/cva6/vendor/pulp-platform/common_cells/src/cdc_2phase.sv 
/home/cva6/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv 
/home/cva6/vendor/pulp-platform/common_cells/src/spill_register.sv 
/home/cva6/vendor/pulp-platform/common_cells/src/deprecated/fifo_v1.sv 
/home/cva6/vendor/pulp-platform/common_cells/src/deprecated/fifo_v2.sv 
/home/cva6/vendor/pulp-platform/common_cells/src/stream_delay.sv 
/home/cva6/vendor/pulp-platform/common_cells/src/lfsr_16bit.sv 
/home/cva6/vendor/pulp-platform/tech_cells_generic/src/deprecated/cluster_clk_cells.sv 
/home/cva6/vendor/pulp-platform/tech_cells_generic/src/deprecated/pulp_clk_cells.sv 
/home/cva6/vendor/pulp-platform/tech_cells_generic/src/rtl/tc_clk.sv 
/home/cva6/corev_apu/tb/ariane_testharness.sv 
/home/cva6/corev_apu/tb/ariane_peripherals.sv 
/home/cva6/corev_apu/tb/rvfi_tracer.sv 
/home/cva6/corev_apu/tb/common/uart.sv 
/home/cva6/corev_apu/tb/common/SimDTM.sv 
/home/cva6/corev_apu/tb/common/SimJTAG.sv 
+define+ corev_apu/tb/common/mock_uart.sv 
+incdir+corev_apu/axi_node  
--unroll-count 256 -Wall -Werror-PINMISSING -Werror-IMPLICIT -Wno-fatal 
-Wno-PINCONNECTEMPTY -Wno-ASSIGNDLY -Wno-DECLFILENAME 
-Wno-UNUSED -Wno-UNOPTFLAT -Wno-BLKANDNBLK -Wno-style  
-DPRELOAD=1     -LDFLAGS "-L/home/RISCV_TOOLS/lib 
-L/home/cva6/tools/spike/lib 
-Wl,-rpath,/home/RISCV_TOOLS/lib 
-Wl,-rpath,/home/cva6/tools/spike/lib 
-lfesvr -lriscv -ldisasm -lyaml-cpp  -lpthread " 
-CFLAGS "-I/include 
-I/include 
-I/home/cva6/tools/verilator-v5.008/share/verilator/include/vltstd 
-I/home/RISCV_TOOLS/include 
-I/home/cva6/tools/spike/include -std=c++17 
-I/home/cva6/corev_apu/tb/dpi -O3 -DVL_DEBUG 
-I/home/cva6/tools/spike"   --cc --vpi  
+incdir+/home/cva6/vendor/pulp-platform/common_cells/include/  
+incdir+/home/cva6/vendor/pulp-platform/axi/include/  
+incdir+/home/cva6/corev_apu/register_interface/include/  
+incdir+/home/cva6/corev_apu/tb/common/  
+incdir+/home/cva6/vendor/pulp-platform/axi/include/  
+incdir+/home/cva6/verif/core-v-verif/lib/uvm_agents/uvma_rvfi/  
+incdir+/home/cva6/verif/core-v-verif/lib/uvm_components/uvmc_rvfi_reference_model/  
+incdir+/home/cva6/verif/core-v-verif/lib/uvm_components/uvmc_rvfi_scoreboard/  
+incdir+/home/cva6/verif/core-v-verif/lib/uvm_agents/uvma_core_cntrl/  
+incdir+/home/cva6/verif/tb/core/  
+incdir+/home/cva6/core/include/  
+incdir+/home/cva6/tools/spike/include/disasm/ 
--top-module ariane_testharness --threads-dpi none --Mdir work-ver -O3 
--exe corev_apu/tb/ariane_tb.cpp 
corev_apu/tb/dpi/SimDTM.cc 
corev_apu/tb/dpi/SimJTAG.cc 
corev_apu/tb/dpi/remote_bitbang.cc 
corev_apu/tb/dpi/msim_helper.cc

执行命令


/home/cva6//work-ver/Variane_testharness   /home/cva6/verif/sim/out_2025-03-17/directed_tests/add.uw-01.o +tb_performance_mode+debug_disable=1+UVM_VERBOSITY=UVM_NONE +ntb_random_seed=962261837 \
  ++/home/cva6/verif/sim/out_2025-03-17/directed_tests/add.uw-01.o +elf_file=/home/cva6/verif/sim/out_2025-03-17/directed_tests/add.uw-01.o +core_name=cv64a6_imafdc_sv39  +tohost_addr=0000000080009000 +signature=/home/cva6/verif/sim/out_2025-03-17/directed_tests/add.uw-01.o.signature_output +UVM_TESTNAME=uvmt_cva6_firmware_test_c +report_file=/home/cva6/verif/sim/out_2025-03-17/veri-testharness_sim/rv64i_m-add.uw-01.cv64a6_imafdc_sv39.log.yaml +core_name=cv64a6_imafdc_sv39 +UVM_VERBOSITY=UVM_NONE
This emulator compiled with JTAG Remote Bitbang client. To enable, use +jtag_rbb_enable=1.
Listening on port 39643
/home/cva6/verif/sim/out_2025-03-17/directed_tests/add.uw-01.o *** SUCCESS *** (tohost = 0) after 22515 cycles
UVM_INFO  @                    0 ns : ariane_testharness Set UVM_VERBOSITY to UVM_NONE
*** [rvfi_tracer] INFO: Simulation terminated after      22503 cycles!

CPU time used: 11035.83 ms
Wall clock time passed: 11033.24 ms
# If present, move default waveform files to log directory.
# Keep track of target in waveform file name.
[ ! -f verilator.fst ] || mv verilator.fst `dirname /home/cva6/verif/sim/out_2025-03-17/veri-testharness_sim/rv64i_m-add.uw-01.cv64a6_imafdc_sv39.log`/`basename /home/cva6/verif/sim/out_2025-03-17/veri-testharness_sim/rv64i_m-add.uw-01.cv64a6_imafdc_sv39.log .log`.fst
[ ! -f verilator.vcd ] || mv verilator.vcd `dirname /home/cva6/verif/sim/out_2025-03-17/veri-testharness_sim/rv64i_m-add.uw-01.cv64a6_imafdc_sv39.log`/`basename /home/cva6/verif/sim/out_2025-03-17/veri-testharness_sim/rv64i_m-add.uw-01.cv64a6_imafdc_sv39.log .log`.vcd
# Generate disassembled log.
/home/cva6/tools/spike/bin/spike-dasm --isa=rv64gc_zba_zbb_zbs_zbc < ./trace_rvfi_hart_00.dasm > /home/cva6/verif/sim/out_2025-03-17/veri-testharness_sim/rv64i_m-add.uw-01.cv64a6_imafdc_sv39.log
grep 0x0000000080000000 ./trace_rvfi_hart_00.dasm
3 0x0000000000010004 (0x01f41413) x 8 0x0000000080000000
core   0: 0x0000000080000000 (0xfeedc0b7) DASM(feedc0b7)
3 0x0000000080000000 (0xfeedc0b7) x 1 0xfffffffffeedc000
3 0x0000000080000728 (0x01ff1f13) x30 0x0000000080000000
3 0x0000000080000cb8 (0x01ff1f13) x30 0x0000000080000000
3 0x00000000800011d4 (0x01fe9e93) x29 0x0000000080000000
3 0x00000000800016a4 (0x01ff1f13) x30 0x0000000080000000
3 0x0000000080008868 (0x01fe9e93) x29 0x0000000080000000