第二十二期-ARMv8-A存储模型概述(2)

作者:罗宇哲,中国科学院软件研究所智能软件研究中心

上一期中我们介绍了ARMv8-A架构中的地址转换机制和访问控制机制,这一期我们将考察ARMv8-A架构中的应用级内存模型(Application Level Memory Model)。

一、ARMv8-A架构的应用内存模型

应用级内存模型指的是从应用软件的视角来观察和操作处理器的内存行为而形成的模型。ARM v8-A 架构中的内存主要有两种类型:

  • Normal类型:对该种类型的内存可以进行常见的读写操作或只读操作,系统中大部分内存都是这种类型;
  • Device类型:对该种类型的内存进行读写可能具有连带效应(side-effects,指对一个内存位置的读写操作会影响其它内存位置)或者从该种内存中的一个位置装载的值可能随着装载的次数而变化。通常内存映射外设(指使用访问内存的方法来访问的外设)会采用这种内存类型。

Normal类型和Device类型的内存有不同的内存属性[2]:
在这里插入图片描述
上表中Shareability是与一致性有关的内存属性,用来指示一个内存位置对于一些处理器是否是可共享的。共享意味着需要硬件保证一个内存位置中的内容对一定范围内可访问该位置的多个处理器是一致。Shareability属性有Non-shareable、Inner Shareable和Outer Shareable三个选项,其含义为:

  • Non-shareable:该内存位置一般只能被唯一处理器访问,如果还有其他处理器能访问该位置,可能需要软件用缓存一致性指令
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This manual describes the ARM® architecture v8, ARMv8. The architecture describes the operation of an ARMv8-A Processing element (PE), and this manual includes descriptions of: • The two Execution states, AArch64 and AArch32. • The instruction sets: — In AArch32 state, the A32 and T32 instruction sets, that are compatible with earlier versions of the ARM architecture. — In AArch64 state, the A64 instruction set. • The states that determine how a PE operates, including the current Exception level and Security state, and in AArch32 state the PE mode. • The Exception model. • The interprocessing model, that supports transitioning between AArch64 state and AArch32 state. • The memory model, that defines memory ordering and memory management. This manual covers a single architecture profile, ARMv8-A, that defines a Virtual Memory System Architecture (VMSA). • The programmers’ model, and its interfaces to System registers that control most PE and memory system features, and provide status information. • The Advanced SIMD and floating-point instructions, that provide high-performance: — Single-precision and double-precision floating-point operations. — Conversions between double-precision, single-precision, and half-precision floating-point values. — Integer, single-precision floating-point, and in A64, double-precision vector operations in all instruction sets. — Double-precision floating-point vector operations in the A64 instruction set. • The security model, that provides two security states to support secure applications. • The virtualization model, that support the virtualization of Non-secure operation. • The Debug architecture, that provides software access to debug features.

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