FGPA 130实例-->problem 5.3~5.15

最新推荐文章于 2024-06-26 20:15:00 发布

liuer2004_82

最新推荐文章于 2024-06-26 20:15:00 发布

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用initial过程语句对测试变量a,b,c赋值

module test;

   reg a,b,c;
   initial
       begin
           a= 0; b= 1;c= 0;
       #50 a= 1; b= 0;
       #50 a= 0; c= 1;
       #50 b= 1;
       #50 b= 0; c= 0;
       #50 $finish;
       end
endmodule

用fork-join并行块产生信号波形

module wave2;
   reg wave;
   parameter cl=5;
   initial
       fork
                  wave=0;
       #(2*cl) wave=1;
       #(3*cl) wave=0;
       #(4*cl) wave=1;
       #(5*cl) wave=0;
       join
endmodule

持续赋值方式定义的2选1多路选择器

module mux21_1(out,a,b,sel);
   output out;
   input a,b,sel;
   assign out=((sel==1'b1)?a:b);
   //assign out=((sel==1'b0)?a:b);
endmodule

阻塞赋值方式定义的2选1多路选择器

module mux21_2(out,a,b,sel);
   output out;
   input a,b,sel;
   reg out;
   always @ (a or b or sel)
       begin
           if (sel==1'b0)
               out=a;
           else
               out=b;
       end
endmodule

非阻塞赋值

module non_block(c,b,a,clk);
   output c,b;
   input a;
   input clk;
   reg c,b;

   always @ (posedge clk)
       begin
           b<=a;
           c<=b;
       end
endmodule

阻塞赋值

module block(c,b,a,clk);
   output c,b;
   input a;
   input clk;
   reg c,b;

   always @ (posedge clk)
       begin
           b=a;
           c=b;
       end
endmodule

模为60的BCD码加法计数器

module count60(qout,cout,data,load,reset,cin,clk);
   output [7:0] qout;
   reg [7:0] qout;
   output cout;
   reg cout;
   input [7:0] data;
   input load,reset,cin,clk;

   always @ (posedge clk)
       begin
           cout=1'd0;
           if(!reset) qout<=8'd0;
           else if(load) qout<=data;
           else
               begin
               if(qout[3:0]!=4'd9) qout[3:0]=qout[3:0]+4'd1;
               else
                   begin
                   qout[3:0]=0;
                   if(qout[7:4]!=4'd5) qout[7:4]=qout[7:4]+4'd1;
                   else
                       begin
                       qout[7:4]=4'd0;
                       cout=1'd1;
                       end
                   end
               end
       end
endmodule

BCD码-七段数码管显示译码器

module decode4_7(decodeout,indec);
   output [7:0] decodeout;
   reg [7:0] decodeout;
   input [3:0] indec;
   always @ (indec)
       begin
           case(indec)
           4'd0:decodeout<=7'b0000000;
           4'd1:decodeout=7'b1111001;
           4'd2:decodeout=7'b0100100;
           4'd3:decodeout=7'b0110000;
           4'd4:decodeout=7'b0011001;
           4'd5:decodeout=7'b0010010;
           4'd6:decodeout=7'b0000010;
           4'd7:decodeout=7'b1111000;
           4'd8:decodeout=7'b0000000;
           4'd9:decodeout=7'b0010000;
           default: decodeout=7'bx;
           endcase
       end
endmodule

用for语句描述的七人投票表决器

module vote7(pass,vote);
   output pass;
   reg pass;
   input [6:0] vote;
   reg [2:0] sum;
   integer i;

   always @ (vote)
       begin
           sum=0;
           for (i=0;i<7;i=i+1)
           if(vote[i]) sum=sum+1;
           if(sum[2]) pass=1'b1;
               else pass=1'b0;
       end
endmodule