Xilinx FPGA:vivado测试Moore与mealy的区别序列检测：“101“

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最新推荐文章于 2024-10-08 15:34:29 发布

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`timescale 1ns / 1ps
/*
测试Moore与mealy的区别   序列检测："101"
*/
module test_moore_mealy(
    input           sysclk          ,
    input           rst_n           ,
    input           din             ,
    output  reg     vaild_re        ,
    output  reg     vaild_ly        
    );
///moore
localparam          IDLE    = 3'd0;
localparam          D_1     = 3'd1;
localparam          D_10    = 3'd3;
localparam          D_101   = 3'd4;
reg     [2:0]       cur_state1,next_state1;
//ate1
always@(posedge sysclk)
    if(!rst_n)
        cur_state1 <= IDLE;
    else
        cur_state1 <= next_state1;
//ate2
always@(*)
    case(cur_state1)
         IDLE  : begin
            if(din == 1)
                next_state1 = D_1;
            else
                next_state1 = cur_state1;
         end   
         D_1   :begin
            if(din == 0)
                next_state1 = D_10;
            else
                next_state1 = cur_state1;
         end 
         D_10  :begin
            if(din == 1)
                next_state1 = D_101;
            else
                next_state1 = IDLE;
         end 
         D_101 :begin
            if(din == 1)
                next_state1 = D_1;
            else
                next_state1 = D_10;
         end
         default:;  
    endcase
//ate3
always@(posedge sysclk)
    if(!rst_n)
        vaild_re <= 0;
    else
        case(cur_state1)
             IDLE  : vaild_re <= 0;
             D_1   : vaild_re <= 0;
             D_10  : vaild_re <= 0;
             D_101 : vaild_re <= 1; 
             default:;         
        endcase  
///mealy
localparam          IDLE_ly    = 3'd0;
localparam          D_1_ly     = 3'd1;
localparam          D_10_ly    = 3'd3;
reg     [2:0]       cur_state2,next_state2;
//ate1
always@(posedge sysclk)
    if(!rst_n)
        cur_state2 <= IDLE_ly;
    else
        cur_state2 <= next_state2;
 //ate2
always@(*)
    case(cur_state2)
         IDLE_ly  : begin
            if(din == 1)
                next_state2 = D_1_ly;
            else
                next_state2 = cur_state2;
         end   
         D_1_ly   :begin
            if(din == 0)
                next_state2 = D_10_ly;
            else
                next_state2 = cur_state2;
         end 
         D_10_ly  :begin
            if(din == 1)
                next_state2 = D_1_ly;
            else
                next_state2 = IDLE_ly;
         end 
         default:;  
    endcase
//ate3
always@(posedge sysclk)
    if(!rst_n)
        vaild_ly <= 0;
    else
        case(cur_state2)
             IDLE_ly  : vaild_ly <= 0;
             D_1_ly   : vaild_ly <= 0;
             D_10_ly  : vaild_ly <= (cur_state2 == D_10_ly && din == 1) ? 1 : 0;
             default:;         
        endcase   
endmodule