有一块板子,我在之上搞了一个视频输入、输出,本人初接FPGA,完全以cpu、dsp方式看FPGA,对于IP类极不适应,看别人弄FPGA鼠标轻点,一会功夫就建立起来一个系统,真是羡慕啊。
我模仿也搭建一个:
输入输出完全是手工编码:
输入:
always@(posedge rx_clk or negedge rst_n) //实用
begin
if ((rst_n == 0) || (M_AXI_ARESETN == 0 ))begin
rx_df <= `F_SDE;
ptr_fd <= 3'd0;
d_page <= 2'd0;
linebytes<=32'd0;
linebyte <=32'd0;
d_pages <=32'd0;
r1234 <= 3'd1;
f_width <= 'h308;
f_higth <= 'd288;
ptr_d <= 'd0;
len_con_a <= 'd0;
rx_1234 <= 'd1;
end else begin
rx_dv_er = 1'b0;
if ((rx_dv == 1'b1) & (rx_er == 1'b0)) begin
rxd = rx_d;
rx_dv_er = 1'b1;
if (rx_df == `F_SDE) begin
case (ptr_fd)
3'd0:begin
if ( (rxd == 16'hc54a) || (rxd == 16'hc53a) ) begin
if (rxd == 16'hc54a)
ptr_fd = ptr_fd + 3'd1;
else ptr_fd = ptr_fd + 3'd3;
end
else ptr_fd = 3'd0;
end
3'd1:
if (rxd == 16'ha34c) //a34c
ptr_fd = ptr_fd + 3'd1;
else ptr_fd = 3'd0;
3'd2: begin
if (rxd == 16'hc54a) begin//c54a
ptr_fd = ptr_fd + 3'd3;
isDL = 1'd1;
end
else ptr_fd = 3'd0;
end
3'd3:
if (rxd == 16'ha35c) //a34c
ptr_fd = ptr_fd + 3'd1;
else ptr_fd = 3'd0;
3'd4: begin
if (rxd == 16'hc53a) begin//c54a
ptr_fd = ptr_fd + 3'd1;
isDL = 1'd0;