路径:trunk\bsp\kernel5.4\kernel5.4\drivers\gpu\drm\sprd\qogirn6pro\global_dpu.c
const struct dpu_clk_ops qogirn6pro_dpu_clk_ops = {
.parse_dt = dpu_clk_parse_dt,
.init = dpu_clk_init,
.enable = dpu_clk_enable,
.disable = dpu_clk_disable,
};
static int dpu_clk_init(struct dpu_context *ctx)
{
int ret;
u32 dpu_core_val;
u32 dpi_src_val;
struct clk *clk_src;
struct dpu_clk_context *clk_ctx = &dpu_clk_ctx;
struct sprd_dpu *dpu = (struct sprd_dpu *)container_of(ctx,
struct sprd_dpu, ctx);
dpu_core_val = calc_dpu_core_clk();
if (dpu->dsi->ctx.dpi_clk_div) {
pr_info("DPU_CORE_CLK = %u, DPI_CLK_DIV = %d\n",
dpu_core_val, dpu->dsi->ctx.dpi_clk_div);
} else {
dpi_src_val = calc_dpi_clk_src(ctx->vm.pixelclock);
pr_info("DPU_CORE_CLK = %u, DPI_CLK_SRC = %u\n",
dpu_core_val, dpi_src_val);
pr_info("dpi clock is %lu\n", ctx->vm.pixelclock);
}
clk_src = val_to_clk(clk_ctx, dpu_core_val);
ret = clk_set_parent(clk_ctx->clk_dpu_core, clk_src);
if (ret)
pr_warn("set dpu core clk source failed\n");
if (dpu->dsi->ctx.dpi_clk_div) {
clk_src = div_to_clk(clk_ctx, dpu->dsi->ctx.dpi_clk_div);
ret = clk_set_parent(clk_ctx->clk_dpu_dpi, clk_src);
if (ret)
pr_warn("set dpi clk source failed\n");
} else {
clk_src = val_to_clk(clk_ctx, dpi_src_val);
ret = clk_set_parent(clk_ctx->clk_dpu_dpi, clk_src);
if (ret)
pr_warn("set dpi clk source failed\n");
ret = clk_set_rate(clk_ctx->clk_dpu_dpi, ctx->vm.pixelclock);
if (ret)
pr_err("dpu update dpi clk rate failed\n");
}
return ret;
}