HDLBits_第2章_Combination Logic(已完结)

目录

Circuits

2 Combinational Logic

2.1 Basic Gates

2.1.1 wire

2.1.2 GND

2.1.3 NOR

2.1.4 Another gate

2.1.5 Two gates

2.1.6 More logic gates

2.1.7 7420 chip

2.1.8 Truth tables

2.1.9 Two-bit equality

2.1.10 Simple circuit A

2.1.11 Simple circuit B

2.1.12 Combine circuits A and B

2.1.13 Ring or vibrate?

2.1.14 Thermostat

2.1.15 3-bit population count

2.1.16 Gates and vectors

2.1.17 Even longer vectors

2.2 Multiplexers

2.2.1 2-to-1 multiplexer

2.2.2 2-to-1 bus multiplexer

2.2.3 9-to-1 multiplexer

2.2.4 256-to-1 multiplexer

2.2.5 256-to-1 4-bit multiplexer

2.3 Arithmetic Circuits 

2.3.1 Half adder

2.3.2 Full adder

2.3.3 3-bit binary adder

2.3.4 Adder

2.3.5 Signed addition overflow

2.3.6 100-bit binary adder

2.3.7 4-digit BCD adder

2.4 Karnaugh Map to Circuit

2.4.1 3-variable

2.4.2 4-variable

2.4.3 4-variable

2.4.4 4-variable

2.4.5 Minimum SOP and POS

2.4.6 Karnaugh map

2.4.7 Karnaugh map

2.4.8 K-map implemented with a multiplexer

---

Circuits

2 Combinational Logic

2.1 Basic Gates

2.1.1 wire

Implement the following circuit:

module top_module (
    input in,
    output out);
	assign out = in;
endmodule

2.1.2 GND

Implement the following circuit:

module top_module (
    output out);
	assign out = 1'b0;
endmodule

2.1.3 NOR

Implement the following circuit:

module top_module (
    input in1,
    input in2,
    output out);
    assign out = ~ (in1 | in2);
endmodule

2.1.4 Another gate

Implement the following circuit:

module top_module (
    input in1,
    input in2,
    output out);
    assign out = in1 & (~in2);
endmodule

2.1.5 Two gates

Implement the following circuit:

module top_module (
    input in1,
    input in2,
    input in3,
    output out);
    assign out = ~(in1 ^ in2) ^ in3;
endmodule

2.1.6 More logic gates

Ok, let's try building several logic gates at the same time. Build a combinational circuit with two inputs, a and b.

There are 7 outputs, each with a logic gate driving it:

• out_and: a and b                
• out_or: a or b
• out_xor: a xor b
• out_nand: a nand b
• out_nor: a nor b
• out_xnor: a xnor b
• out_anotb: a and-not b

module top_module( 
    input a, b,
    output out_and,
    output out_or,
    output out_xor,
    output out_nand,
    output out_nor,
    output out_xnor,
    output out_anotb
);
    assign out_and 	= a & b;            //与门
    assign out_or 	= a | b;            //或门
    assign out_xor	= a ^ b;            //异或门
    assign out_nand = ~(a & b);         //与非门
    assign out_nor  = ~(a | b);         //或非门
    assign out_xnor = ~(a ^ b);         //异或非门；同或门
    assign out_anotb= a & ~b;           //与门，其中b经过反转
endmodule

2.1.7 7420 chip

The 7400-series integrated circuits are a series of digital chips with a few gates each. The 7420 is a chip with two 4-input NAND gates.

Create a module with the same functionality as the 7420 chip. It has 8 inputs and 2 outputs.

module top_module ( 
    input p1a, p1b, p1c, p1d,
    output p1y,
    input p2a, p2b, p2c, p2d,
    output p2y );
    assign p1y = ~(p1a & p1b & p1c & p1d);
    assign p2y = ~(p2a & p2b & p2c & p2d);
endmodule

2.1.8 Truth tables

In the previous exercises, we used simple logic gates and combinations of several logic gates. These circuits are examples of combinational circuits. Combinational means the outputs of the circuit is a function (in the mathematics sense) of only its inputs. This means that for any given input value, there is only one possible output value. Thus, one way to describe the behaviour of a combinational function is to explicitly list what the output should be for every possible value of the inputs. This is a truth table.

前面的练习中，我们使用了简单逻辑门和几个逻辑门的组合。这些电路都是组合电路的例程。组合电路意味着电路的输出在函数中仅有一个输出（数字意义上）。这意味着对于任意给定的输入值，都有唯一可能的输出值。因此，描述组合函数行为的其中一种方法就是显式地将每个输入列出对应的每个可能的输出值。这就是真值表。

For a boolean function of N inputs, there are 2N possible input combinations. Each row of the truth table lists one input combination, so there are always 2N rows. The output column shows what the output should be for each input value.

对于一个有N个输入的布尔函数，有2的N次方种可能的输入组合。真值表的每一行列举了其中一种可能的输入，所有总共有2的N次方行。输出列显示每个输入值应该输出什么。

The above truth table is for a three-input, one-output function. It has 8 rows for each of the 8 possible input combinations, and one output column. There are four inputs combinations where the output is 1, and four where the output is 0.

以上真值表是3输入1输出的函数。其有8种输入组合方式，对应8列的输出值。其有4种输入会使输出为1，4种输入组合会使输出为0

Synthesizing a circuit from a truth table

Suppose we want to build the above circuit, but we're limited to using only the set of standard logic gates. How would you build arbitrary logic functions (expressed as a truth table)?

假设我们想要构建上述电路，但被限制，只能使用一种标准的逻辑门。如何构建任意逻辑函数？（实现真值表对应的功能）

One simple method to create a circuit that implements the truth table's function is to express the function in sum-of-products form. Sum (meaning OR) of products (meaning AND) means using one N-input AND gate per row of the truth table (to detect when the input matches each row), followed by an OR gate that chooses only those rows that result in a '1' output.

创建实现真值表功能电路的一种简单方法就是使用乘积和的形式表示函数。sum（或）of products（与），意味着再真值表的每一行使用一个n输入的与门（检测输入是否匹配这一行），后面跟着一个or门，只选择那些输出为1的行。

For the above example, the output is '1' if the input matches row 2 or row 3 or row 5 or row 7 (This is a 4-input OR gate). The input matches row 2 if x3=0 and x2=1 and x1=0 (This is a 3-input AND gate). Thus, this truth table can be implemented in canonical form by using 4 AND gates that are ORed together.

对于上面的示例，如果输入时第2、3、5、7行（4输入或门），则输出为1.如果x3=0、x2=1、x1=0则输入匹配第2行（这是一个3输入与门）。因此，这个真值表可以通过使用4个or的AND门来实现。

A Bit of Practice

Create a combinational circuit that implements the above truth table.

module top_module( 
    input x3,
    input x2,
    input x1,  // three inputs
    output f   // one output
);             // 将4种输出为1的输入组合相"与"
    assign f = ((~x1)&x2&(~x3)) | (x1&x2&(~x3)) | (x1&(~x2)&x3) | (x1&x2&x3);
endmodule

2.1.9 Two-bit equality

Taken from 2015 midterm question 1k

Create a circuit that has two 2-bit inputs A[1:0] and B[1:0], and produces an output z. The value of z should be 1 if A = B, otherwise z should be 0.

module top_module ( input [1:0] A, input [1:0] B, output z ); 
    assign z = (A == B) ? 1 : 0;
endmodule

2.1.10 Simple circuit A

Taken from 2015 midterm question 4

Module A is supposed to implement the function z = (x^y) & x. Implement this module.

module top_module (input x, inp