openofdm 01：Power Trigger

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已于 2023-01-28 20:49:32 修改

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分类专栏： openofdm 文章标签： fpga开发

于 2023-01-24 13:55:37 首次发布

本文链接：https://blog.csdn.net/m0_46521579/article/details/128756065

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本文介绍了OpenOFDM中Power Trigger模块的工作原理，该模块接收I/Q样本并检测潜在的包活动期间的触发信号。在硬件稳定阶段可以跳过初始样本以避免杂散信号。模块主要包含三个状态：S_SKIP、S_IDLE和S_PACKET，并根据设定的阈值、窗口大小和采样点数进行功率检测和触发信号的产生。

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It takes the I/Q samples as input and asserts the trigger signal during a potential packet activity.

Optionally, it can be configured to skip the first certain number of samples before detecting a power trigger. This is useful to skip the spurious signals during the initial hardware stabilization phase.

The logic of the power_trigger module is quite simple: after skipping certain number of initial samples, it waits for significant power increase and triggers the trigger signal upon detection. The trigger signal is asserted until the power level is smaller than a threshold for certain number of continuous samples.

    input clock,                //时钟
    input enable,               //模块使能
    input reset,                //复位

    input set_stb,              //设置选通信号
    input [7:0] set_addr,       //设置地址，8位
    input [31:0] set_data,      //设置数据，32位

    input [31:0] sample_in,     //采样输入，32位
    input sample_in_strobe,     //采样输入选通信号

    output reg trigger          //触发信号

先通过setting_reg模块设置set_stb、set_addr和set_data等相关参数：（1）信号检测阈值[15:0] power_thres；（2）信号消失检测窗口长度[15:0] window_size；（3）信号出现时跳过的采样点数目[31:0] num_sample_to_skip。

power_thres = 16'd100;

window_size = 16'd80;

num_sample_to_skip = 32'd0; //原来是32‘d500_0