verilog——三八译码器

三八译码器

`timescale 1ns / 1ps
module three28(
    a,
    b,
    c,
    out
    );
    input a;
    input b;
    input c;
    output reg [7:0] out;//always里赋值必须是reg型
    
    
    //always描述的信号赋值，赋值对象必须是reg类型
    always@(*)
    begin
        case({a,b,c})         //{a,b,c}就是变成了一个三位信号，位拼接
           3'b000:out = 8'b00000001;
           3'b001:out = 8'b00000010;
           3'b010:out = 8'b00000100;
           3'b011:out = 8'b00001000;
           3'b100:out = 8'b00010000;
           3'b101:out = 8'b00100000;
           3'b110:out = 8'b01000000;
           3'b111:out = 8'b10000000;
         endcase
    end
endmodule

test_bench代码

`timescale 1ns/1ps
module three28_tb();
    
    reg a;
    reg b;
    reg c;
    wire [7:0]out;
    
    ///例化
    three28 three28_test(
    .a(a),
    .b(b),
    .c(c),
    .out(out)
    );       
    
    initial begin
        a=0;b=0;c=0;
        #200;
        a=0;b=0;c=1;
        #200;
        a=0;b=1;c=0;
        #200;
        a=0;b=1;c=1;
        #200;
        a=1;b=0;c=0;
        #200;
        a=1;b=0;c=1;
        #200;
        a=1;b=1;c=0;
        #200;
        a=1;b=1;c=1;
        #200;
        $stop;//结束仿真
    end

endmodule