ECC的点乘顶层代码

 

module PAdd_TOP( 
 CLK, 
 RST_N, 
 DIN_P0_x, 
 DIN_P0_y, 
 DIN_P1_x, 
 DIN_P1_y, 
 DOUT_P2_x, 
 DOUT_P2_y, 
 IN_VALID, 
 OUT_VALID 
) 
… 
PAdd_FSM pa_fsm( 
 .CLK(CLK), 
 .RST_N(RST_N), 
 .P0_x_Load(P0_x_Load), 
 .P0_x_Clear(P0_x_Clear), 
 .P0_y_Load(P0_y_Load), 
 .P0_y_Clear(P0_y_Clear), 
 .P1_x_Load(P1_x_Load), 
 .P1_x_Clear(P1_x_Clear), 
 .P1_y_Load(P1_y_Load), 
 .P1_y_Clear(P1_y_Clear),
.reg_add1_out_Load(add1_out_Load), 
 .reg_add1_out_Clear(add1_out_Clear), 
 .INV_IN_VALID(INV_IN_VALID), 
 .INV_OUT_VALID(INV_OUT_VALID), 
 .reg_inv_out_Load(inv_out_Load), 
 .reg_inv_out_Clear(inv_out_Clear), 
 .reg_add2_out_Load(add2_out_Load), 
 .reg_add2_out_Clear(add2_out_Clear), 
 .reg_mult1_out_Load(mult1_out_Load), 
 .reg_mult1_out_Clear(mult1_out_Clear), 
 .reg_mult2_out_Load(mult2_out_Load), 
 .reg_mult2_out_Clear(mult2_out_Clear), 
 .reg_add5_out_Load(add5_out_Load), 
 .reg_add5_out_Clear(add5_out_Clear), 
 .MULT1_IN_VALID(mult1_IN_VALID), 
 .MULT1_OUT_VALID(mult1_OUT_VALID), 
 .MULT2_IN_VALID(mult2_IN_VALID), 
 .MULT2_OUT_VALID(mult2_OUT_VALID), 
 .AP_OUT_STATE(ap_OUT_STATE) 
 ); 
always @(posedge CLK) 
 if(!RST_N) 
 begin 
 DIN_P0_x_temp <= 0; 
 DIN_P0_y_temp <= 0; 
 DIN_P1_x_temp <= 0; 
 DIN_P1_y_temp <= 0; 
 cnt_top <= 0; 
 end 
 
 else if(IN_VALID) 
 begin 
 DIN_P0_x_temp <= DIN_P0_x; 
 DIN_P0_y_temp <= DIN_P0_y; 
 DIN_P1_x_temp <= DIN_P1_x; 
 DIN_P1_y_temp <= DIN_P1_y; 
 end 
 else 
 begin 
 DIN_P0_x_temp <= 0; 
 DIN_P0_y_temp <= 0; 
 DIN_P1_x_temp <= 0; 
 DIN_P1_y_temp <= 0; 
 cnt_top <= cnt_top + 1;
end 
always @(posedge CLK) 
 if((ap_OUT_STATE == 3'b100) && (mult2_OUT_VALID == 1'b1)) 
 begin 
 DOUT_P2_x <= DOUT_add4; 
 DOUT_P2_y <= DOUT_add7; 
 OUT_VALID <= 1'b1; 
 end 
 else if(cnt_top == 13) 
 begin 
 …… 
 end 
 else 
 begin 
 DOUT_P2_x <= 0; 
 DOUT_P2_y <= 0; 
 OUT_VALID <= 1'b0; 
 end 
endmodule