48位，53位阵列乘法器verilog实现（3,6,12,24位乘法器以及相关加法器可在之前文章查看）

module mult53(A,B,S);
	input	[52:0]A,B;
	output	[105:0]S;

	wire[95:0] a,b;//96位乘法器
	wire[191:0] s;
	wire	[95:0]stage11,stage12,stage13,stage14;
	wire	[95:0]stage2;
	wire	stage2_c;
	wire	[95:0]stage31,stage32;

	assign a={{43{1'b0}},A};//输入的53位前面补43位0，可组成96位
	assign b={{43{1'b0}},B};
	//Stage1
	mult48	block1(a[47:0],b[47:0],stage11);
	mult48	block2(a[47:0],b[95:48],stage12);
	mult48	block3(a[95:48],b[47:0],stage13);
	mult48	block4(a[95:48],b[95:48],stage14);

	//Stage2
	adder96  block5(.A(stage12),.B(stage13),.S(stage2),.Cout(stage2_c));

	//Stage3
	adder96	block6(.A({{48{1'b0}},stage11[95:48]}),.B(stage2),.S(stage31),.Cout());
	adder96	block7(.A(stage14),.B({{48{1'b0}},stage2_c,stage31[95:48]}),.S(stage32),.Cout());

	assign	s = {stage32,stage31[47:0],stage11[47:0]};
	assign  S= s[105:0];
	endmodule
///ok
module mult48(A,B,S);
	input	[47:0]A,B;
	output	[95:0]S;

	wire	[47:0]stage11,stage12,stage13,stage14;
	wire	[47:0]stage2;
	wire	stage2_c;
	wire	[47:0]stage31,stage32;

	//Stage1
	mult24	block1(A[23:0],B[23:0],stage11);
	mult24	block2(A[23:0],B[47:24],stage12);
	mult24	block3(A[47:24],B[23:0],stage13);
	mult24	block4(A[47:24],B[47:24],stage14);

	//Stage2
	adder48  block5(.A(stage12),.B(stage13),.S(stage2),.Cout(stage2_c));

	//Stage3
	adder48	block6(.A({{24{1'b0}},stage11[47:24]}),.B(stage2),.S(stage31),.Cout());
	adder48	block7(.A(stage14),.B({{23{1'b0}},stage2_c,stage31[47:24]}),.S(stage32),.Cout());

	assign	S = {stage32,stage31[23:0],stage11[23:0]};

endmodule
///ok

可仿真，可综合