Query Server 和Yield Server 在IC上的使用

最近一直在研究两件事，目前都有了一些成果。

第一件事：不同版图EDA工具间数据的转换问题，除了基于OA的database的pcell 还是存在一些各家工具自己封闭的内容，这部分内容如何能够不同tool上做对应。

因为目前主流foundry都会提高两套PDK，所以这部分foundry提供ipdk的一般问题都不大。这里不展开说。

第二件事：如果使用验证工具来完善版图上的设计流程。

这里举个例子：如果版图没有完全使用SDL 这样的设计Flow来做，后期导致net 和device 没法和电路上一一对应。这个问题有没有办法解决。Virtuoso 配合pvs 可以重塑SDL对应关系 Custom compiler 配合ICV同样可以实现SDL的关系。CC中对于的command是：

lx：：establishCorrespondenceFromLVS -path <lvs run path> -layout <dmcellview> -schematic <dmschematic>

如果使用第三方工具做的PV 是否也能够实现这样的功能。看过我文章的应该看到过前面提到的calibre的perc，perc确实可以实现从lvs pass的svdb 或dfmdb结果中提取出device信息，net信息。但是我感觉还不够方便。今天介绍的calibre的 queryServer 和YieldServer 能够更快的提取出这些信息。DRC LVS可能大家比较熟悉对query和yield 比较陌生，这两个server在某些场景下也是非常好用，也很方便。

对应的命令是calibre -qs 和calibre -ys

从calibre svdb结果到Custom compiler重建SDL也是基于query和Yield 来实现的。

下面列举个case演示qs 和ys 的部分功能，

这个case是使用YieldServer 的脚本来实现Hierarchy的报告

set cells [dfm::get_cells];
while {$cells != ""} {
 set cellName [dfm::get_data $cells -cell_name];
 lappend cellList $cellName;
 dfm::inc cells;
}
# get the total cell count
set cellCount [llength $cellList];
# test for hierarchy and exit if there is none
if { $cellCount < "2" } {
 puts "\n NOTE: Layout has no hierarchy. Nothing to do. \n";
 exit 0;
} 
# put any debug diagnostics here
if { [info exists DEBUG] == 1 } { 
 puts "\n---$cellCount layout cells: \n\n[regsub -all { } \
[lsort $cellList] "\n"] \n";
};
proc hier_count { cells level } { 
# if this proc is called, there is an additional level of hierarchy
 incr level; 
 set currentCells $cells;
 set newCells "";
# track cells at a given level
 foreach child $currentCells { 
 append newCells "[dfm::list_children $child] ";
 } 
 if { [lindex $newCells 0] != "" } {
 hier_count $newCells $level;
 } else {
 return $level;
 }
} 
puts "\n\n CELL HIERARCHY LEVELS AND INSTANTIATIONS"
puts "---------------------------------------------------------------\n";
# iterate over all cells.
set hierList "";
foreach cell $cellList {
 set plCount [dfm::get_placement_count $cell]
 set childCells [dfm::list_children $cell]
# if there are child cells, process to find the number of hierarchy 
# levels, otherwise add to the list with hierarchy as <0>
 if { [llength $childCells] > 0 } {
 lappend hierList [list $cell "levels: [hier_count "$childCells" 0]"\
"instantiations: $plCount"];
 } else {
 lappend hierList [list $cell "levels: 0" "instantiations: $plCount"];
 }
}
# output the cell list in ascii order
# create a 3-column matrix for printing
struct::matrix m0;
m0 add columns 3;
set sortList [lsort $hierList];
set sortListLength [llength $sortList];
for {set i 0} {$i < $sortListLength} {incr i} {
# if struct::matrix is not available, use next line for output instead
# puts "---[lindex $sortList $i]";
 m0 add row "---[lindex $sortList $i]";
}
# output the table
m0 format 2chan;
puts "\n";
proc write_tree { level {cell ""} {indent ""} } { 
 if { $cell == 0 } {
 puts "\n ERROR: Cannot determine top cell.";
 exit 1;
 }
# get placements in a cell
 set pl [dfm::get_placements $cell]
# write the cell placement in the tree
 puts "$indent <$level> $cell"; 
# adjust the indent level of the tree
 append indent " ";
# increment the level
 incr level; 
# recursively call this proc to descend all branches of the hierarchy
 while {$pl != ""} {
 set plName [dfm::get_data $pl -cell_name];
 write_tree $level $plName $indent;
 dfm::inc pl;
 } 
} 
# OUTPUT FROM THIS PART IS VERBOSE! UNCOMMENT TO CALL IT.
# puts "\n\n HIERARCHY TREE"
# puts "-------------------------------------------------------------\n";
# call the write_tree proc. hierarchy level is 0 beginning with top cell
# write_tree 0 [dfm::get_top_cell]; # UNCOMMENT TO WRITE TREE;
puts "\n\n---Done.\n"
exit -force
}

效果：

CELL HIERARCHY LEVELS AND INSTANTIATIONS

---------------------------------------------------------------

Loading hierarchy and connectivity

---CellA levels: 1 instantiations: 2

---CellB levels: 1 instantiations: 1

---TOPCELL levels: 2 instantiations: 0

---inv levels: 0 instantiations: 1

---nand levels: 0 instantiations: 2

HIERARCHY TREE

---------------------------------------------------------------

 <0> TOPCELL

 <1> CellA

 <2> nand

 <1> CellA

 <2> nand

 <1> CellB

 <2> inv