VHDL——异步清除十进制加法计数器

library ieee;
use ieee.std_logic_1164.all;

entity adderT is
    port(clr : in std_logic;
	      clk : in std_logic;
	      cnt : buffer integer range 9 downto 0);
end adderT;

architecture behavior of adderT is
begin
process(clr,clk)
    begin
	 if clr = '0' then cnt <= 0;
	 elsif clk'event and clk='1' then --clk为上升沿	
	     if (cnt = 9) then --当cnt加到9时，继续增加则清零
		      cnt <= 0;
		  else
		      cnt <= cnt + 1;
		  end if;
	 end if;
end process;
end behavior;